SPI CS glitch
Posted: Fri Oct 12, 2018 3:06 pm
I am working with SPI interface in master mode
This is my peripheral configuration
My application transmit only four bytes periodically to slave device (device_addr+reg_addr+reg_data+reg_data)
I check my code with EPS32 devboard without any device connected to SPI pins I have connect only the analyzer probes for checking the message format and sometimes I see a little glitch in a random postion in the SPI_CS pin (I attach two images) The glitch is 20ns wide. When the SPI slave peripheral detect a CS change state reset the communication in progress and tx message fail. I dont know if there are more wide glitch on SPI_CS but I am worried.
My salve peripheral (disconnected at the moment) is an I/O expander MCP23S17 and datasheet say min CS hold time 50ns I think the 20ns glitch can't be detect but if sometime the glitch is more wide...
This is my peripheral configuration
Code: Select all
#define PIN_NUM_MISO 19
#define PIN_NUM_MOSI 23
#define PIN_NUM_CLK 18
#define PIN_NUM_CS 5
spi_bus_config_t buscfg={
.miso_io_num=PIN_NUM_MISO,
.mosi_io_num=PIN_NUM_MOSI,
.sclk_io_num=PIN_NUM_CLK,
.quadwp_io_num=-1,
.quadhd_io_num=-1
};
spi_device_interface_config_t devcfg={
.clock_speed_hz = 10*100*1000, //Clock out at 1 MHz
.mode = 0, //SPI mode 0
.spics_io_num = PIN_NUM_CS, //CS pin
.queue_size = 3, //We want to be able to queue 7 transactions at a time
.pre_cb = 0,
};
//Initialize the SPI bus
ret=spi_bus_initialize(VSPI_HOST, &buscfg, 0);
assert(ret==ESP_OK);
ret=spi_bus_add_device(VSPI_HOST, &devcfg, &mcp23x17.spi);
assert(ret==ESP_OK);
Code: Select all
// wirte out
memset (&t, 0, sizeof(t)) ;
t.tx_data[0] = (MCP23x17_ADDRESS << 1) + 0x00 ;
t.tx_data[1] = MCP23x17_OLATA ;
t.tx_data[2] = outA ;
t.tx_data[3] = outB ;
t.flags = SPI_TRANS_USE_TXDATA ;
t.length = 8*(1+1+1+1) ;
ret = spi_device_transmit(mcp23x17.spi, &t); //Transmit!
assert(ret==ESP_OK); //Should have had no issues.
I check my code with EPS32 devboard without any device connected to SPI pins I have connect only the analyzer probes for checking the message format and sometimes I see a little glitch in a random postion in the SPI_CS pin (I attach two images) The glitch is 20ns wide. When the SPI slave peripheral detect a CS change state reset the communication in progress and tx message fail. I dont know if there are more wide glitch on SPI_CS but I am worried.
My salve peripheral (disconnected at the moment) is an I/O expander MCP23S17 and datasheet say min CS hold time 50ns I think the 20ns glitch can't be detect but if sometime the glitch is more wide...