'Spurious watchdog reset at power up'
Posted: Wed Jul 25, 2018 4:23 pm
I am working with a ESP32-D0WD device (small package) and I get some time to time some problems at power up. If I run the 'serial monitor', I see in these cases that I have a double reset :
rst:0x1 (POWERON_RESET),boot:0x3b (SPI_FAST_FLASH_BOOT)
ets Jun 8 2016 00:22:57
rst:0x10 (RTCWDT_RTC_RESET),boot:0x2f (UART_BOOT(UART0))
and my application is frozen, waiting for some input at the UART0... Most of times, my application stats properly, but not always.
I am working with a 1.8V FLASH and I burned the efuse bits to force the regulator voltage at 1.8V (checked on the Vcc pin of the FLASH).
This issue looks like the first problem described in the errata list: https://www.espressif.com/sites/default ... p32_en.pdf : spurious reset at power up...
But does this 'old issue' also apply to the new D0WD (october 2017) ? Is the only workaround consists in writing a program for the ULP ?
I am also wondering if the timing at the 'CHIP_PU' is important. I have on my board RC=1k x 100nF. Is it a correct value ?
When I check in the EFUSE summary, I find:
CHIP_VER_REV1 Silicon Revision 1 = 0 R/W (0x0)
CHIP_VERSION Reserved for future chip versions = 0 R/W (0x0)
CHIP_PACKAGE Chip package identifier = 1 R/W (0x1)
Does it mean that my device is still a revision 0 ?
Thanks for your help ?
FrancisL
rst:0x1 (POWERON_RESET),boot:0x3b (SPI_FAST_FLASH_BOOT)
ets Jun 8 2016 00:22:57
rst:0x10 (RTCWDT_RTC_RESET),boot:0x2f (UART_BOOT(UART0))
and my application is frozen, waiting for some input at the UART0... Most of times, my application stats properly, but not always.
I am working with a 1.8V FLASH and I burned the efuse bits to force the regulator voltage at 1.8V (checked on the Vcc pin of the FLASH).
This issue looks like the first problem described in the errata list: https://www.espressif.com/sites/default ... p32_en.pdf : spurious reset at power up...
But does this 'old issue' also apply to the new D0WD (october 2017) ? Is the only workaround consists in writing a program for the ULP ?
I am also wondering if the timing at the 'CHIP_PU' is important. I have on my board RC=1k x 100nF. Is it a correct value ?
When I check in the EFUSE summary, I find:
CHIP_VER_REV1 Silicon Revision 1 = 0 R/W (0x0)
CHIP_VERSION Reserved for future chip versions = 0 R/W (0x0)
CHIP_PACKAGE Chip package identifier = 1 R/W (0x1)
Does it mean that my device is still a revision 0 ?
Thanks for your help ?
FrancisL