esp32 c5 seems woefully short on SRAM

[bill1davis]

384K versus 520K for the original esp32 seems really tight. can someone at espressif shed some light on this? Are the restrictions about declaring task stacks that do crypto or tcp/ip or flash operations now lifted? Is there a bunch more usable SRAM on these parts than on the original esp32 due to code changes? Am I missing something in the docs? I haven't found a production rev datasheet for the C5.

[bill1davis]

Answering my own question, I have learned that newer idfs can be configured to copy rom to spiram at boot time, which should eliminate the restrictions on task stacks that hit the rom, using the following :

SPIRAM_FETCH_INSTRUCTIONS: This configuration parameter allows moving instructions from flash to PSRAM. If enabled, instructions in flash will be moved into PSRAM on startup. If SPIRAM_RODATA parameter is also enabled, the code that normally requires execution during the SPI1 flash operation does not need to be placed in IRAM, thus optimizing RAM usage. By default, this parameter is disabled.

When CONFIG_SPIRAM_XIP_FROM_PSRAM is enabled, the flash.text sections (for instructions) and the .rodata section (read only data) will be moved to PSRAM. Corresponding virtual memory range will be mapped to PSRAM. Under this condition, ESP-IDF won't disable concurrent accesses to external memory (SET1 operations) anymore.

By using this feature, during SET2 operations, placement of ISRs, ISR callbacks, and related data are no longer limited to internal RAM.