ESP32 Forum

Trying to decide if we really need LDO regulators and IC switches based on our testing results.

1. The datasheet specifies the max power voltage as 3.6VDC, but I have used up to 4.15 VDC in testing prototypes for a year with no problems. Is the max still 3.6VDC?

2. We understand there is no DAC in the Esp32s3. The datasheet specifies the GPIO logic "high" voltage out as from .75*VDD to VDD+.3, which is a pretty wide variance. But we have seen consistently VDD as "high" output voltage in our GPIO output testing. We noted that the output voltage is apparently programmatically controlled in the Sigma-Delta Modulation coding example in Espressif IDE but it's not clear what the voltage (amplitude) range is. We have been using logic high which is at VDD to turn on some low power devices with no problems detected but not sure if logic high at VDD is consistent. How can we assure ourselves of a consistent logic "high".

We can use LDOs and switches to set and control the voltages into our low power devices but would prefer to just use logic high and lows if the output voltages are consistently at the appropriate levels.

jjones7432 wrote: ↑

Wed Jul 17, 2024 10:09 pm

Trying to decide if we really need LDO regulators and IC switches based on our testing results.

1. The datasheet specifies the max power voltage as 3.6VDC, but I have used up to 4.15 VDC in testing prototypes for a year with no problems. Is the max still 3.6VDC?

Yes. We're not saying that the chips absolutelywon't work above that rating, but we're saying we don't guarantee what happens then. Might be that they're perfectly fine, might be that only some modules will work, might be that they don't work over the entire temperature range, might be that a subtle process change makes it so newer modules all break when fed that way. No way of telling since we don't guarantee anything at those higher voltages. For all we know, an ESP32 ran at that voltage gains sentience and tries to take over the world or something.

2. We understand there is no DAC in the Esp32s3. The datasheet specifies the GPIO logic "high" voltage out as from .75*VDD to VDD+.3, which is a pretty wide variance. But we have seen consistently VDD as "high" output voltage in our GPIO output testing. We noted that the output voltage is apparently programmatically controlled in the Sigma-Delta Modulation coding example in Espressif IDE but it's not clear what the voltage (amplitude) range is. We have been using logic high which is at VDD to turn on some low power devices with no problems detected but not sure if logic high at VDD is consistent. How can we assure ourselves of a consistent logic "high".

Those ranges (and note you're quoting the input range, the output is 0.1Vdd to 0.8Vdd) are generally specified under the allowable loads. If you want to be an absolutist about this, the same thing goes as with the supply voltage: we only guarantee what's in the datasheet. But a GPIO is a lot easier to understand, and generally you can assume that if the load on your GPIOs is negligable compared to the max current rating, you'll get voltages that are very close to the voltage rails. If you want to be absolutely sure, you'd need some sort of external chip (logic-level inverter, level shifter, whatever) that can output voltages that have tighter specs.

We can use LDOs and switches to set and control the voltages into our low power devices but would prefer to just use logic high and lows if the output voltages are consistently at the appropriate levels.

Note that a delta-sigma GPIO is not a LDO; it does not have a feedback loop.

Looking at the datasheet you can find that, at Vdd=3.3V, high output pins can source up to 40mA while maintaining a voltage of >= 2.64V (=0.8*Vdd).
'Assuming' FETs are used inside the ESP to drive the outputs, you can estimate the upper limit for the (high level) output impedance of the pins to be (3.3V-2.64V)/0.04A = 16.5 Ohms. With that figure you may be able to determine if the GPIOs are sufficient for supplying power to your other chips.