ESP32 Forum

There are SPI_USER_REG (0x1C) flags SPI_WR_BYTE_ORDER and SPI_RD_BYTE_ORDER, switching endianess of Tx and Rx data.

When SPI MISO stream is following:
from left to right: 00 49 4A F0 80 00, with default settings SPI transaction field rx_buffer gets MISO data exactly in the order from left to right.

Which effect will cause SPI_RD_BYTE_ORDER when enabled?
Does it depend on DMA or not?
How to enable these options in spi master driver?

hi
https://github.com/espressif/esp-idf/bl ... i_master.h
spi_device_interface_config.flags

ok-home wrote: ↑

Mon Jun 17, 2024 4:35 am

hi
https://github.com/espressif/esp-idf/bl ... i_master.h

Code: Select all

#define SPI_DEVICE_TXBIT_LSBFIRST          (1<<0)  ///< Transmit command/address/data LSB first instead of the default MSB first
#define SPI_DEVICE_RXBIT_LSBFIRST          (1<<1)  ///< Receive data LSB first instead of the default MSB first
#define SPI_DEVICE_BIT_LSBFIRST            (SPI_DEVICE_TXBIT_LSBFIRST|SPI_DEVICE_RXBIT_LSBFIRST) ///< Transmit and receive LSB first

spi_device_interface_config.flags

so, byte order remains the same, and bits within bytes get reversed
thanks