Timing Parameters for the Strapping Pins
Posted: Tue Mar 26, 2024 1:46 pm
Hi Espressif Community:
The ESP32-S3 datasheet describes the setup time and hold time timing for the strapping pins.
https://www.espressif.com/sites/default ... eet_en.pdf
2.6 Strapping Pins
Figure 2-4: Visualization of Timing Parameters for the Strapping Pins
tSU: Setup time is described as from VIH of Strapping pin to VIL_nRST of CHIP_PU.
Is this correct from VIH of Strapping pin to "VIH_nRST" of CHIP_PU?
I checked the signal waveforms of GPIO0 and CHIP_PU on ESP32-S3-DevkitC-1 when power is turned on,
The VIL_nRST of CHIP_PU from VIH of Strapping pin does not satisfy the condition of tSU,
The condition of tSU is satisfied by "VIH_nRST" from VIH to CHIP_PU of Strapping pin.
As for the Boot Mode of ESP32-S3-DevkitC-1, as described in Table 2-11, Chip Boot Mode Control,
it seems to operate normally with SPI Boot by identifying GPIO0 as 1.
Thanks,
N.N
The ESP32-S3 datasheet describes the setup time and hold time timing for the strapping pins.
https://www.espressif.com/sites/default ... eet_en.pdf
2.6 Strapping Pins
Figure 2-4: Visualization of Timing Parameters for the Strapping Pins
tSU: Setup time is described as from VIH of Strapping pin to VIL_nRST of CHIP_PU.
Is this correct from VIH of Strapping pin to "VIH_nRST" of CHIP_PU?
I checked the signal waveforms of GPIO0 and CHIP_PU on ESP32-S3-DevkitC-1 when power is turned on,
The VIL_nRST of CHIP_PU from VIH of Strapping pin does not satisfy the condition of tSU,
The condition of tSU is satisfied by "VIH_nRST" from VIH to CHIP_PU of Strapping pin.
As for the Boot Mode of ESP32-S3-DevkitC-1, as described in Table 2-11, Chip Boot Mode Control,
it seems to operate normally with SPI Boot by identifying GPIO0 as 1.
Thanks,
N.N