About the CAN controller.

[ESP_Sprite]

Okay, documentation won't be forthcoming any time soon, but I may be able to drop some info that allows you to experiment with the CAN driver.

The good part is that I can probably give you enough information to create a driver for the thing: The CAN driver we use basically is compatible with the SJA1000 CAN controller. According to what I received, the base register is 0x3FF6B000 and the interrupt source in the int mux are defined in soc/soc.h in esp-idf as ETS_CAN_INTR_SOURCE. Its output pins are defined in the GPIO_MUX documentation and header files. The controller is powered off until you tweak the correct bits in DPORT_PERIP_CLK_EN_REG and DPORT_PERIP_RST_EN_REG to enable it. If you write to the CAN registers, you may get bitten by a SoC bug in the first revision of the silicon that's out now: if you write the registers too quickly, the 2nd write may be discarded. This can be alleviated by putting a volatile asm(("nop;nop;nop;nop;nop;nop;nop;nop;"); line between writes, if memory serves. I'm not sure if the CAN controller is affected by this, but it may be good to keep this in mind.

The bad part is that we have tested absolutely nothing wrt the CAN controller yet. The implementation we chose itself is ASIC-tested, but not on this chip, so there may be issues there. If you decide to go messing with the CAN controller, please be aware that you may run into silicon bugs; if you do, please tell us and we'll see if we can fix them in the next metal revision.

Also, if any of you happen to create a driver that is also an esp-idf component, of reasonable code quality and you are willing to license it under the Apache 2.0 license, we're happy to include it in esp-idf for general use.

Feel free to use this topic to post additional questions; while I don't want to spend too much developer and hardware engineer time on it, I'll see what I can do to answer them.

[rudi ;-)]

Its output pins are defined in the GPIO_MUX documentation and header files.

hi jeroen
not sure, but can you point me please to this - GPIO_MUX Docu
i know only this : http://espressif.com/sites/default/file ... t_en_0.pdf
and technical reference manual : http://espressif.com/sites/default/file ... ual_en.pdf

if you mean other ( named CAN pins ) please let me know.
( CAN_Rx, CAN_Tx, CAN_DATA0...CAN_DATA7 ...)
or we can create own PIN Names what we need and MUX to GPIO then.

second:
not sure,
we use the same BIT in same Register for two difference function?
or have we difference Register?
Can you point me to the Register Docu / MUX `?
Or small bug?

https://github.com/espressif/esp-idf/bl ... reg.h#L940

Code: Select all

..
#define DPORT_CAN_CLK_EN   (BIT(19))

https://github.com/espressif/esp-idf/bl ... reg.h#L974

Code: Select all

..
#define DPORT_CAN_RST      (BIT(19))
..

third:

volatile asm(("nop;nop;nop;nop;nop;nop;nop;nop;");

i will use this for delaying between first and next write to register

Code: Select all

__asm__ __volatile__("nop;nop;nop;nop;nop;nop;nop;nop;");

ok?

thanks for clear words and helps


best wishes
rudi

Have we small more detailed Infos about
DPORT_PRO_CAN..
DPORT_APP_CAN..
DPORT_AHBLITE_MPU_TABLE_CAN..

Code: Select all

#define DPORT_PRO_CAN_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x1B8)
/* DPORT_PRO_CAN_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_CAN_INT_MAP  0x0000001F
#define DPORT_PRO_CAN_INT_MAP_M  ((DPORT_PRO_CAN_INT_MAP_V)<<(DPORT_PRO_CAN_INT_MAP_S))
#define DPORT_PRO_CAN_INT_MAP_V  0x1F
#define DPORT_PRO_CAN_INT_MAP_S  0

#define DPORT_APP_CAN_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x2CC)
/* DPORT_APP_CAN_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_APP_CAN_INT_MAP  0x0000001F
#define DPORT_APP_CAN_INT_MAP_M  ((DPORT_APP_CAN_INT_MAP_V)<<(DPORT_APP_CAN_INT_MAP_S))
#define DPORT_APP_CAN_INT_MAP_V  0x1F
#define DPORT_APP_CAN_INT_MAP_S  0

#define DPORT_AHBLITE_MPU_TABLE_CAN_REG          (DR_REG_DPORT_BASE + 0x3C0)
/* DPORT_CAN_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
/*description: */
#define DPORT_CAN_ACCESS_GRANT_CONFIG  0x0000003F
#define DPORT_CAN_ACCESS_GRANT_CONFIG_M  ((DPORT_CAN_ACCESS_GRANT_CONFIG_V)<<(DPORT_CAN_ACCESS_GRANT_CONFIG_S))
#define DPORT_CAN_ACCESS_GRANT_CONFIG_V  0x3F
#define DPORT_CAN_ACCESS_GRANT_CONFIG_S  0

[WiFive]

Its output pins are defined in the GPIO_MUX documentation and header files.

Half right?

https://github.com/espressif/esp-idf/bl ... _sig_map.h

[rudi ;-)]

Its output pins are defined in the GPIO_MUX documentation and header files.

Half right?

https://github.com/espressif/esp-idf/bl ... _sig_map.h

thanks WiFive

Code: Select all

#define CAN_RX_IDX	94
#define CAN_TX_IDX	123
#define CAN_BUS_OFF_ON_IDX	124
#define CAN_CLKOUT_IDX	125

[rudi ;-)]

had a try
used the new uart driver too..
Short YT_Video : ESP32 CAN EMU testings ( unofficially doings )
now need small infos for build registers and ...more

best wishes
rudi

[rudi ;-)]

short back questions for right BASE things thinking:

DPORT_AHBLITE_MPU_TABLE_CAN_REG


AHB means Advanced High-performance Bus, right?
and is part of the Advanced Microprocessor Bus Architecture (AMBA).

AHB-Lite.png (32.03 KiB) Viewed 36272 times

we do not mean APB - ( Advanced Peripheral Bus )
(AHB uses a full duplex parallel communication whereas the APB uses massive memory-I/O accesses )

full duplex means Full-duplex right ?

what is mean with "LITE" in the define?
is it mean like the bus architecture,
have we limits exampl. think "Half-duplex" but not "simplex" right?

or other thing?

is AHB-Lite Bridge theme used in this?

would be nice for small info so can start with this DPORT_AHBLITE faster

thanks!
best wishes
rudi


found a hint:

DPORT_AHBLITE_MPU_TABLE.png (60.08 KiB) Viewed 36270 times

taken from last technical reference: [ S. 162 ]

esp32_technical_reference_manual_en.pdf

(2.52 MiB) Downloaded 1870 times

Each bit of register DPORT_AHBLITE_MPU_TABLE_X_REG determines whether each process can access the
peripherals managed by the register. For details please see Table 54. When a bit of register
DPORT_AHBLITE_MPU_TABLE_X_REG is 1, it means that a process with the corresponding PID can access the
corresponding peripheral of the register. Otherwise, the process cannot access the corresponding
peripheral.

[WiFive]

AHB-lite is a simplified version of the full AMBA 2 AHB specification, supporting only a single Master.

I don't think MPU is usable yet. Are you having problems with CAN register access ?

[rudi ;-)]

AHB-lite is a simplified version of the full AMBA 2 AHB specification, supporting only a single Master.

Yes this do ARM tell, i try to clear the things that we speak from same
ok - i have AMBA now in the eyes, there is AMBA TM Spec 2.0 online
AMBA
spec 2.0

amba.pdf

(1.83 MiB) Downloaded 1472 times

Design infos spec 3.0 ( AMBA 3.0 (AXI) )

V3.0_IJSRON2013542.pdf

(175.44 KiB) Downloaded 1335 times

small VERI LOG BackInfo too [S. 2 ]
( AHB-LITE PROTOCOL SYSTEM )

IJET16-08-02-081.pdf

(458.52 KiB) Downloaded 1290 times

I don't think MPU is usable yet. Are you having problems with CAN register access ?

start this week with this - hope get few infos here collected next day about this and that for working.
the info in the techn. reference docu on last side is to small but can help with "standard EMU" things,
not the first try in this but knowing about existing bugs / workarounds can save time

stay tuned this thread - have wait for this CAN theme.
have not see earliest, jeroen wrote end of october this theme,
hope he see the replies that we HOT interessted in this


best wishes
rudi

append following
with 2 resources cause limit is 3 files / post

[rudi ;-)]

10.1.1.302.239.pdf

AHB Blocks [ S. 3 ]

(1.6 MiB) Downloaded 1363 times

148-468-1-PB.pdf

AMBA AHB to AXI Bus

(542.61 KiB) Downloaded 1326 times

[WiFive]

I don't think you need to know about AMBA.

Did you try assuming register set is approx same as SJA1000?

http://lxr.free-electrons.com/source/dr ... /sja1000.h