ESP32 Forum

Hello,

In the deep sleep mode, if we power up the XTAL, I was curious if it's possible for the ULP to access the 40 MHz XTAL as RTC_FAST_CLK.

In the header soc/clk_tree_defs.h, there appears to be an option.

/**
* @brief RTC_FAST_CLK mux inputs, which are the supported clock sources for the RTC_FAST_CLK
* @note Enum values are matched with the register field values on purpose
*/
typedef enum {
SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 0, /*!< Select XTAL_D2_CLK (may referred as XTAL_CLK_DIV_2) as RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
SOC_RTC_FAST_CLK_SRC_RC_FAST = 1, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */
} soc_rtc_fast_clk_src_t;


I did test switching to the RTC_FAST_CLK.

The way the test is setup is such that I am continuously transmitting data to one of the GPIO and I am able to detect the data coming out through an LED blinking.

When I switch from RTC_FAST_CLK to RTC_SLOW_CLK, the LED blinks slower, confirming that the test works.

When I switch the clock source itself for RTC_FAST_CLK to the XTAL_D2_CLK, I stop getting signals.

I used the following registers to power up the XTAL and make the switch
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING, 1);
REG_SET_FIELD(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU, 1);
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL, 0);

It would be wonderful if I could use the XTAL that is already in the ESP32-S3-WROOM-1 module instead of putting in an optional external 32kHz XTAL.

Please let me know if this could be done.