ESP32S3 (WROOM) I2S question
Posted: Wed Jan 10, 2024 5:55 pm
Hello,
I am new to the ESP32 family but not new to embedded software programming. I am trying to get the I2S bus to work with MEMS microphone.
I have configured the I2S as follow:
During boot, I see the following messages:
Even the BCLK signal is not quite right. When the WS signal transition to high, the BCLK signal has a glitch (attachment #1)
Where should I look next?
Thanks.
I am new to the ESP32 family but not new to embedded software programming. I am trying to get the I2S bus to work with MEMS microphone.
I have configured the I2S as follow:
- i2s_std_config_t std_cfg = {
- .clk_cfg = I2S_STD_CLK_DEFAULT_CONFIG(48000),
- .slot_cfg = I2S_STD_MSB_SLOT_DEFAULT_CONFIG(I2S_DATA_BIT_WIDTH_32BIT, I2S_SLOT_MODE_STEREO),
- .gpio_cfg = {
- .mclk = PIN_I2S_MCLK,
- .bclk = PIN_I2S_BCLK,
- .ws = PIN_I2S_WS,
- .dout = I2S_GPIO_UNUSED,
- .din = PIN_I2S_DIN,
- .invert_flags = {
- .mclk_inv = false,
- .bclk_inv = false,
- .ws_inv = false,
- },
- },
- };
But when I look at the signal with the logic analyzer, I am seeing some bizarre things (see attachment #2). The WS signal is not good when low but is right when high.I (300) mems: Starting the I2S bus
D (301) i2s_common: rx channel is registered on I2S0 successfully
D (301) i2s_common: MCLK is pinned to GPIO0 on I2S4
D (302) i2s_common: DMA malloc info: dma_desc_num = 6, dma_desc_buf_size = dma_frame_num * slot_num * data_bit_width = 1920
D (303) i2s_std: Clock division info: [sclk] 160000000 Hz [mdiv] 13 [mclk] 12288000 Hz [bdiv] 4 [bclk] 3072000 Hz
D (305) i2s_std: The rx channel on I2S0 has been initialized to STD mode successfully
D (306) i2s_common: i2s rx channel enabled
Even the BCLK signal is not quite right. When the WS signal transition to high, the BCLK signal has a glitch (attachment #1)
Where should I look next?
Thanks.