ESP32 Forum

Hello,

can somebody explain details about the I2S_TIMING_REG register values (see 12.8 in
the datasheet?

Especially concerning the following:

• what are the cycles referenced for e.g. I2S_RX_SD_IN_DELAY . Is it BCK cycles? or I2Sn_CLK cycles?
• what is the meaning of I2S_RX_DSYNC_SW? which signals are double synchronized? on which clock?
• is there any timing diagram which shows the effect of the I2S_TIMING_REG values?

Thanks a lot for any help and clarification

best regards
Fabian