ESP32 Forum

Hey all,

I'm trying to design a board around an esp module, not carrying so much which chip is used but do want to have a certain peripherals.

A simple list of requirements:
I need an Ethernet MAC interface, ideally RMII as that saves a lot of pins and is quite well documented on how to use (RTL8201F is for example a good candidate for the PHY).
Secondly, the ESP module will speak to a serial device, which communicates with hardware flow control (RTS/CTS, so this is not an optional feature) at a fixed baud rate of 1Mbit, though for discussion sake, lets assume it talks at 5Mbit, which is the ESP's max.
Thirdly, I need flash to store the application, PXE booting is not an option, but if there's alternative's I'm happy to hear.
Finally, a module is best, as it contains the PCB antenna and is pre-certified. This is quite important :p

However the combination's I'm after, do not seem to compute

First of all, it seems only the ESP32 seems to have an Ethernet MAC, so I've been looking mostly at the WROOM variant.

Here we have our RMII capable Ethernet MAC, great. However, if we want to have hardware flow control, the options become more difficult. UART1 as a whole, is on the same pins as the flash. Why these pins are exposed, baffles me a little, though I suppose alternative QSPI users, on a 2nd Chip select could be used ...

UART2's RTS and CTS are also shared with the flash pinout.

Then there's UART0, which could be used for both scenario's, e.g. only use it for the control of my device, but when in bootloader mode, it falls back into programming mode. The signals are used for their intended use, just the software configures the port at different speeds, no problem to me (the other end might not like seeing strings at the incorrect speed, but we'll see). However, the CTS and RTS are shared with TXD0 and TXD1 of the ethernet MAC. WHY I cringe, why are they not on the TXD2 and TXD3 if they must be there :p So those are not an option either.

I'm not sure if we can use the direct IO mapping for the TX/RX pins, but use the GPIO matrix for the RTS/CTS and what the performance impact is thereof? The manual seems to warn us for high-speed usage to avoid the GPIO matrix. And since all 4 pins are available here, I would expect that at 1+ Mbit, this matters, but here the documentation lacks information.

At what speeds is it wise to use the direct IO mux?
Can we map the CTS/RTS on any GPIO pin via the GPIO mux, while keeping the RX and TX on the IO mux?

Is there truly no other ESP chip with ethernet MAC? The product selector seems to say so ...

Thanks,

Do not be afraid to use GPIO Matrix function to map UART to any available GPIO. Since UART is not a very high speed interface, you will not lose too much speed if you do not use GPIOs in IO MUX. Then I think you could use ESP32 modules to realize all your requirements.

Thanks @ESP_LJH, however I intend to use the UART at 1Mbit - 5Mbit, which is the maximum baudrate the ESP supports. At these speeds, I do feel that it becomes important? If not, why are they mapped to the iomux pins at all, with a warning about this in the manual?

Since a PHY also costs money, I'm now actually more favoring ENC28J60 based solutions, which just require an SPI bus. True, the chip is more expensive then just the PHY, but since the ESP32 is the only variant with a MAC, and the pin-combinations are not ideal/useable, might aswell, allowing me to use any MCU pretty much, inc. the risc-v based ESP's or 8266

oliv3r wrote: ↑

Mon Nov 06, 2023 10:00 am

Thanks @ESP_LJH, however I intend to use the UART at 1Mbit - 5Mbit, which is the maximum baudrate the ESP supports. At these speeds, I do feel that it becomes important? If not, why are they mapped to the iomux pins at all, with a warning about this in the manual?

It's generally not an issue until like 20MHz or so. Things like the SPI will have a different issue in that the latency of the GPIO matrix plays a role there, but an asynchronous protocol like UART doesn't suffer from that.

So then 'why' are the UART pins brought out on the IOmatrix, with the note on the iomatrix 'important for high-speed signals'. If it doesn't matter, shouldn't it not have mattered and not be part of the iomatrix at all? It's a bit misleading/confusing to 'de leek'

I'm not a digital designer, but my guess would be that it's easier to set 'default' pins in silicon using the IOMUX than the GPIO matrix