ESP32-C3 design with external 32.786kHz crystal

[cyber_v1]

Hello!

I'm having trouble with the 32.786kHz crystal; it doesn't start!
One board is Wemos C3 Pico https://www.wemos.cc/en/latest/c3/c3_pico.html; I tried two different crystals, different capacitors, tried to put a resistor in parallel (though the hardware design guidelines document says it must not be needed) - nothing helped.
Another board is a custom board with a crystal from a yet different manufacturer - still no luck.
I checked Espressif's reference designs for the boards using ESP32-C3 but none have the external crystal; is there any reference design with the working 32K crystal? Any recommendations what to check?

Best regards

[cyber_v1]

The capacitors are 15pF each and the crystal is JGHC S3132768092070.
I tried to check with an oscilloscope and I see 32768 Hz oscillations, around 0.4V in amplitude. Is that not enough? The firmware doesn't detect any ticks. What am I missing?

[HamGuy]

Hello,
What does the output look like on the scope with original crystal?
Regards,
Ron

[cyber_v1]

Here you are, using a 10x probe.
AFAIU pin 4 is the "input" of the crystal and pin 5 is the output. So the output is around 0.24V

[MicroController]

I see 32768 Hz oscillations, around 0.4V in amplitude.

I'd take that as a sign that the oscillator in the ESP is successfully running the crystal.

The firmware doesn't detect any ticks.

a) can you post the log output of the chip starting?
b) what "ticks" are you looking at/for?
Did you enable the crystal as the RTC clock source?

[cyber_v1]

The firmware doesn't detect any ticks.

a) can you post the log output of the chip starting?
b) what "ticks" are you looking at/for?

Code: Select all

SPIWP:0xee
mode:DIO, clock div:1
load:0x3fcd5820,len:0x1708
load:0x403cc710,len:0x928
load:0x403ce710,len:0x2c4c
entry 0x403cc710
I (24) boot: ESP-IDF v5.1-dirty 2nd stage bootloader
I (25) boot: compile time Oct  5 2023 21:17:00
I (25) boot: chip revision: v0.4
I (28) boot.esp32c3: SPI Speed      : 80MHz
I (32) boot.esp32c3: SPI Mode       : DIO
I (37) boot.esp32c3: SPI Flash Size : 2MB
I (42) boot: Enabling RNG early entropy source...
I (47) boot: Partition Table:
I (51) boot: ## Label            Usage          Type ST Offset   Length
I (58) boot:  0 nvs              WiFi data        01 02 00009000 00006000
I (66) boot:  1 phy_init         RF data          01 01 0000f000 00001000
I (73) boot:  2 factory          factory app      00 00 00010000 00100000
I (81) boot: End of partition table
I (85) esp_image: segment 0: paddr=00010020 vaddr=3c0b0020 size=34780h (214912) map
I (127) esp_image: segment 1: paddr=000447a8 vaddr=3fc92e00 size=024c8h (  9416) load
I (130) esp_image: segment 2: paddr=00046c78 vaddr=40380000 size=093a0h ( 37792) load
I (140) esp_image: segment 3: paddr=00050020 vaddr=42000020 size=ab0c8h (700616) map
I (253) esp_image: segment 4: paddr=000fb0f0 vaddr=403893a0 size=098f0h ( 39152) load
I (267) boot: Loaded app from partition at offset 0x10000
I (267) boot: Disabling RNG early entropy source...
I (278) cpu_start: Unicore app
I (279) cpu_start: Pro cpu up.
D (279) clk: waiting for 32k oscillator to start up
W (905) 3 2kHz xtal debug: expected_xtal_cycles 25000000
W (905) 3 2kHz xtal debug: delta 125000
W (906) 3 2kHz xtal debug: range 24875000 ~ 25125000
W (910) 3 2kHz xtal debug: actual_xtal_cycles 0
E (915) 3 2kHz xtal debug: error, out of expected range!
D (921) clk: waiting for 32k oscillator to start up
W (1551) 3 2kHz xtal debug: expected_xtal_cycles 25000000
W (1551) 3 2kHz xtal debug: delta 125000
W (1552) 3 2kHz xtal debug: range 24875000 ~ 25125000
W (1556) 3 2kHz xtal debug: actual_xtal_cycles 0
E (1561) 3 2kHz xtal debug: error, out of expected range!
D (1567) clk: waiting for 32k oscillator to start up
W (2197) 3 2kHz xtal debug: expected_xtal_cycles 25000000
W (2198) 3 2kHz xtal debug: delta 125000
W (2198) 3 2kHz xtal debug: range 24875000 ~ 25125000
W (2202) 3 2kHz xtal debug: actual_xtal_cycles 0
E (2208) 3 2kHz xtal debug: error, out of expected range!
D (2214) clk: waiting for 32k oscillator to start up
W (2844) 3 2kHz xtal debug: expected_xtal_cycles 25000000
W (2844) 3 2kHz xtal debug: delta 125000
W (2845) 3 2kHz xtal debug: range 24875000 ~ 25125000
W (2849) 3 2kHz xtal debug: actual_xtal_cycles 0
E (2854) 3 2kHz xtal debug: error, out of expected range!
W (2860) clk: 32 kHz XTAL not found, switching to internal 150 kHz oscillator
D (3171) clk: RTC_SLOW_CLK calibration value: 3870093

The additional "xtal debug" messages are from the patch provided here: https://github.com/espressif/esp-idf/is ... 1671401554. "actual_xtal_cycles 0" means no oscillations were detected.

Did you enable the crystal as the RTC clock source?

Yes, and I also tried to crank up the defaults - didn't have any effect:

Code: Select all

% rg CLK_SRC sdkconfig        
981:# CONFIG_RTC_CLK_SRC_INT_RC is not set
982:CONFIG_RTC_CLK_SRC_EXT_CRYS=y
983:# CONFIG_RTC_CLK_SRC_EXT_OSC is not set
984:# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set
2140:# CONFIG_ESP32C3_RTC_CLK_SRC_INT_RC is not set
2141:CONFIG_ESP32C3_RTC_CLK_SRC_EXT_CRYS=y
2142:# CONFIG_ESP32C3_RTC_CLK_SRC_EXT_OSC is not set
2143:# CONFIG_ESP32C3_RTC_CLK_SRC_INT_8MD256 is not set

% rg CYCLE sdkconfig          
985:CONFIG_RTC_CLK_CAL_CYCLES=20480
1091:CONFIG_ESP_SYSTEM_RTC_EXT_XTAL_BOOTSTRAP_CYCLES=1024
2144:CONFIG_ESP32C3_RTC_CLK_CAL_CYCLES=20480
2155:CONFIG_ESP32_RTC_XTAL_BOOTSTRAP_CYCLES=1024

[MicroController]

Is the log output the same with and without the oscilloscope probe(s) connected?

Btw, the amplitude of the oscillation is not really meaningful. It's basically determined by the hysteresis of the oscillator's input, for which 0.3V seems reasonable. If the amplitude wasn't high enough to 'toggle' the oscillator it wouldn't be oscillating.

[cyber_v1]

Yes, the output is the same with or without the probes.

I don't understand how it's possible. It seems there is some issue with the MCU itself

[cyber_v1]

I have realized something while studying the ESP32-C3 Technical Reference Manual and the source code of esp-idf. I didn't reset the cranked up values between I tested the old board and the custom board
I reset CONFIG_RTC_CLK_CAL_CYCLES to the default of 3000 and it worked!

Code: Select all

D (279) clk: waiting for 32k oscillator to start up
W (371) 3 2kHz xtal debug: expected_xtal_cycles 3662109
W (372) 3 2kHz xtal debug: delta 18310
W (372) 3 2kHz xtal debug: range 3643799 ~ 3680419
W (376) 3 2kHz xtal debug: actual_xtal_cycles 3662047
W (382) 3 2kHz xtal debug: ok!
D (477) clk: RTC_SLOW_CLK calibration value: 15999727

A rough explanation of what happened:
When calibrating the external clock, esp-idf sets TIMG_RTC_CALI_TIMEOUT_THRES in TIMG_RTCCALICFG2_REG to RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(slowclk_cycles), and RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(cycles) is defined as (cycles << 12). The slowclk_cycles is CONFIG_RTC_CLK_CAL_CYCLES from the project configuration, and the API reference states that the range of CONFIG_RTC_CLK_CAL_CYCLES is:

• from 0 to 27000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_8MD256
• from 0 to 32766.

When slowclk_cycles=20480 from my old config was used, RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(cycles) was 20480*4096=0x5000000 but the maximum value of TIMG_RTC_CALI_TIMEOUT_THRES is 0x1ffffff and it overflowed. The remaining piece of mystery is that 0x5000000&0x1ffffff=0x1000000 but as far as I understand, zero threshold was used instead, which lead to the MCU to always report the timeout.

[cyber_v1]

The remaining piece of mystery is that 0x5000000&0x1ffffff=0x1000000 but as far as I understand, zero threshold was used instead, which lead to the MCU to always report the timeout.

I figured this out as well.
TIMG_RTC_CALI_TIMEOUT_THRES was indeed set to 0x1000000. Together with the default TIMG_RTC_CALI_TIMEOUT_RST_CNT=3 and CPU frequency of 160MHz it gave the timeout of 3*2^24/160000000=0.3145728s but with TIMG_RTC_CALI_MAX=20480 it would need 20480/32768=0.625s so it always timed out.