ESP32 :: what is the max I2S parallel read frequency?
Posted: Thu Sep 28, 2023 4:54 pm
Hi,
I'm sort of lost with the poor espressif tech documentation on ESP32.... It does not give any idea what the max frequency is @ which ESP32 I2S can read data in parallel mode (LCD/CAMERA). Is it F_CLK or F_BCK?
ESP32 datasheet only says that I2S is clocked by either PLL_F160M_CLK or configurable APLL.
In either case the clock source goes through the I2S clock divider whose minimum allowable value is 1/2 (section "12.3 The Clock of I2S Module", p.310).
In case PLL_F160M_CLK is used we come up with a max value of 80 MHz.
If we engage APLL we can can get the maximum value of (500MHz / 4) times 1/2 = 125 / 2 = 62.5 MHz (section "3.2.7 Audio PLL", p.44).
Further on section "12.3 The Clock of I2S Module" also says (quotation):
"When ESP32 I2S works in slave mode, the master must use I2Sn_CLK as the master clock and F_I2S >= 8 * F_BCK".
If so, F_BCK appears to be at least 8 times less than F_CLK and we end up with the upmost figures:
(a) F_BCK = F_CLK / 8 = 80 MHz / 8 = 10 MHz or
(b) F_BCK = F_CLK / 8 = 62.5 MHz / 8 = ~7.8 MHz
Am I getting the whole thing right that when we put ESP32 I2S in SLAVE RECV mode the external device should clock ESP32 I2S peripheral @ F_CLK = 80 MHz so that parallel data lines (D0....D15) are read @ F_BCK = 10 MHz at most and we can't read them any faster???????
Or what is the correct way of determining the max parallel read speed and clock frequency in RECV SLAVE mode???????
I'm sort of lost with the poor espressif tech documentation on ESP32.... It does not give any idea what the max frequency is @ which ESP32 I2S can read data in parallel mode (LCD/CAMERA). Is it F_CLK or F_BCK?
ESP32 datasheet only says that I2S is clocked by either PLL_F160M_CLK or configurable APLL.
In either case the clock source goes through the I2S clock divider whose minimum allowable value is 1/2 (section "12.3 The Clock of I2S Module", p.310).
In case PLL_F160M_CLK is used we come up with a max value of 80 MHz.
If we engage APLL we can can get the maximum value of (500MHz / 4) times 1/2 = 125 / 2 = 62.5 MHz (section "3.2.7 Audio PLL", p.44).
Further on section "12.3 The Clock of I2S Module" also says (quotation):
"When ESP32 I2S works in slave mode, the master must use I2Sn_CLK as the master clock and F_I2S >= 8 * F_BCK".
If so, F_BCK appears to be at least 8 times less than F_CLK and we end up with the upmost figures:
(a) F_BCK = F_CLK / 8 = 80 MHz / 8 = 10 MHz or
(b) F_BCK = F_CLK / 8 = 62.5 MHz / 8 = ~7.8 MHz
Am I getting the whole thing right that when we put ESP32 I2S in SLAVE RECV mode the external device should clock ESP32 I2S peripheral @ F_CLK = 80 MHz so that parallel data lines (D0....D15) are read @ F_BCK = 10 MHz at most and we can't read them any faster???????
Or what is the correct way of determining the max parallel read speed and clock frequency in RECV SLAVE mode???????