ESP32 Forum

Hello Espressif Community,

I have two questions related to the PWM hardware of ESP32:

1. By the documentation of the LEDC library, there are 4 timers and 16 PWM channels in ESP32. I would like to ask if all of the 4 timers are ticking at 80 MHz (assume all prescaler is 1).

2. I know that the frequency and resolution of a specific PWM channel are inversely-proportioned. However, I cannot find an exact mathematical formula to describe their relation. For example, if I set the frequency to be 10 kHz, what is the maximum bit count of resolution? How do I calculate that?

Thank you very much for your help.

Aurora wrote: ↑

Fri Aug 11, 2023 1:38 am

1. By the documentation of the LEDC library, there are 4 timers and 16 PWM channels in ESP32. I would like to ask if all of the 4 timers are ticking at 80 MHz (assume all prescaler is 1).

TRM, §14.2.1:
"the LED_PWM controller contains eight high-speed and eight low-speed channels. There are four high-speed clock modules for
the high-speed channels, from which one h_timerx can be selected. There are also four low-speed clock modules
for the low-speed channels, from which one l_timerx can be selected."

§14.2.2:
"Where the high-speed timer clock source can be clocked from REF_TICK or APB_CLK, the low-speed timers
are sourced from either REF_TICK or SLOW_CLOCK. The SLOW_CLOCK source can be either APB_CLK
(80 MHz) or 8 MHz,..."

2. I know that the frequency and resolution of a specific PWM channel are inversely-proportioned. However, I cannot find an exact mathematical formula to describe their relation. For example, if I set the frequency to be 10 kHz, what is the maximum bit count of resolution? How do I calculate that?

If F[clk] is the timer's clock and F[pwm] the PWM frequency and r is the PWM resolution, the following holds:

r = 2 ^ bitcount ("two to the power of bitcount", or in C: 1<<bitcount)

F[pwm] = F[clk] / r = F[clk] / (2 ^ bitcount)

For given F[clk] and F[pwm] the theoretical maximum resolution is

r = F[clk] / F[pwm]

The required bit count is the log2 of the theoretical resolution; ex.:

F[clk] = 80'000'000Hz
F[pwm] = 10'000Hz
->
r = 8000

log2(r) ~ 12.97... bits

So for F[pwm] not less than 10kHz, you need a bit count not greater than 12.97..., i.e. the maximum bit count value permissible to achieve (at least) the given F[pwm] is 12 in the example.

The actual resolution you get is then 2^12 = 4096 steps, the actual F[pwm] is 80'000'000Hz/4096 ~ 19.5kHz.
If you chose 13 bits (8192 steps), F[pwm] would top out at ~9.77kHz, not quite reaching 10kHz.

Works the other way around too: If you need a resolution of not less than r=5000 steps you get log2(5000) ~ 12.29... bits and you'll need a bit count of not less than 12.29..., so at least 13 (i.e. 8192 steps).