ESP32 Forum

With reference to the following diagrams (Fig-1, Fig-2), I have few questions as given below:
Figure-1:
Figure-2:
Figure-3:

My questions are:
1. Is the Flash Memory (U3) of Fig-3 marked as **External Memory** in Fig-2?
2. Is FreeRTOS firmware pre-installed in "Instruction ROM Memory" of Fig-1? Which core it is -- Core0 or Core1?
3. From where I can have the Pin Diagram along with signal signatures for the LX6 Processor

GolamMostafa wrote: ↑

Sun Jul 23, 2023 3:53 pm

1. Is the Flash Memory (U3) of Fig-3 marked as **External Memory** in Fig-2?

Yes, it is.

GolamMostafa wrote: ↑

Sun Jul 23, 2023 3:53 pm

2. Is FreeRTOS firmware pre-installed in "Instruction ROM Memory" of Fig-1? Which core it is -- Core0 or Core1?

It's not. FreeRTOS (plus every other part of the system: heap implementation, C library, peripheral drivers, network stacks, etc) is compiled along with your application and linked into the application binary. Application binary is stored in Flash. Parts of the application are copied into the internal RAM ("Instruction RAM" and "Data RAM" blocks of Fig.1) on boot, including some parts of FreeRTOS.

GolamMostafa wrote: ↑

Sun Jul 23, 2023 3:53 pm

3. From where I can have the Pin Diagram along with signal signatures for the LX6 Processor

Not sure exactly what you are looking for... There is a pin diagram of the chip, you can find it in the datasheet. However the none of the chip pins are directly connected to the signals of the processor.

Perhaps if you describe the problem you are originally trying to solve I can give a more useful answer, and we can avoid the XY problem.

Thank you very much for the reply. I will come with more queries/questions once I have finished digesting your answers. In the meantime, may I ask the following questions?

1. Is there any off-chip (I mean outside Core) RAM/ROM/Cache memory like the flash memory?
2. Is there a separate bus for the flash memory or the same APB bus is used?
3. Is their any inter-connecting wires between the two cores so that they can interrupt each other?
4. I have read about AHB (Advanced High Performance Bus) in the ChatGPT -- does such bus exist in the EPS32 System?
5. The ChatGPT is also saying that some low bandwidth peripherals like UART and similar are on the APB Bus and high bandwidth peripherals are on the AHB Bus. Which peripherals of the following diagram (Fig-1) are of low bandwidth and which are of high bandwidth?
Figure-1:

GolamMostafa wrote: ↑

Mon Jul 24, 2023 1:47 am

1. Is there any off-chip (I mean outside Core) RAM/ROM/Cache memory like the flash memory?

You can have external PSRAM; otherwise no.

2. Is there a separate bus for the flash memory or the same APB bus is used?
4. I have read about AHB (Advanced High Performance Bus) in the ChatGPT -- does such bus exist in the EPS32 System?
5. The ChatGPT is also saying that some low bandwidth peripherals like UART and similar are on the APB Bus and high bandwidth peripherals are on the AHB Bus. Which peripherals of the following diagram (Fig-1) are of low bandwidth and which are of high bandwidth?

I don't think that information is public.

3. Is their any inter-connecting wires between the two cores so that they can interrupt each other?

Yes, there's a few interrupts that can be triggered by the other CPU. They're used to e.g. halt the other CPU when the flash is inaccessible because e.g. it's being written.

You can have external PSRAM; otherwise no.

As per Secion-1.3.2.1 of Espressif Technical Reference Manual, the ESP32 contains the following memory components; but is does not talk about PSRAM -- is it correct?
440 KiB ROM Memory,
520 KIB SRAM,
8 KIB RTC Fast Memory, and
8 KiB RTC Slow Memory.

Yes, there's a few interrupts that can be triggered by the other CPU. They're used to e.g. halt the other CPU when the flash is inaccessible because e.g. it's being written.

Any sample codes that I can test using Arduino IDE and ESP32S Board for such interruption?

GolamMostafa wrote: ↑

Mon Jul 24, 2023 8:03 am

You can have external PSRAM; otherwise no.

As per Secion-1.3.2.1 of Espressif Technical Reference Manual, the ESP32 contains the following memory components; but is does not talk about PSRAM -- is it correct?

Yes, as ESP_Sprite said, ESP32 hardware supports external memory chips, i.e. FLASH and optionally PSRAM.

Yes, there's a few interrupts that can be triggered by the other CPU.

Any sample codes that I can test using Arduino IDE and ESP32S Board for such interruption?

No. But note that FreeRTOS uses the cross-core interrupt all the time, e.g. when a task or ISR on one core causes a context switch on the other core (via a queue, semaphore, or other synchronization primitive). C.f. https://github.com/espressif/esp-idf/bl ... core_int.c

This is my pleasure to let you know that I have been delivering lectures on "32-Bit Architecture and Programming using 30-pin Dual-Core ESP32S Board" to the undergraduate students of EE Department of my University. This is the reason for me to place queries in order to have my concepts/understandings/assumptions clear and meaningful as much as possible.

It would be very helpful for me if I can have data sheets of LX6 Processor (particularly the pin diagram and signal signatures of the Processor) so that I can build-up a conceptual connection diagram among the Cores and the Peripherals (like UART, Flash Memory, etc.) imposed by Espressif Systems.

GolamMostafa wrote: ↑

Tue Jul 25, 2023 4:45 am

It would be very helpful for me if I can have data sheets of LX6 Processor (particularly the pin diagram and signal signatures of the Processor) so that I can build-up a conceptual connection diagram among the Cores and the Peripherals (like UART, Flash Memory, etc.) imposed by Espressif Systems.

Sorry, that stuff is owned by Cadence (who nowadays own the Xtensa architecture) and we're not allowed to share them.

With reference to the attached diagram (Fig-1, given below), I would like to know, if there is any cache memory that Espressif has installed along with their Mask ROM, RAM, and RTC memory? If yes, how much its capacity and what kind of interface is used to access it (SPI, I2C, UART, ..)?
Figure-1:

If yes, how much its capacity and what kind of interface is used to access it (SPI, I2C, UART, ..)?

If by "cache memory" you mean "flash memory", then the answer is: varying, up to 16 MB possible; accessed via SPI.

If you actually mean "cache", then I'm wondering what kind of "cache" you're talking about that would plausibly be accessed via any serial protocol.

I suggest you refer to the Technical Reference Manual regarding concepts and details of "I-cache" and "D-cache", if that is what your question is about.