ESP32 Forum

I know that there are two LX6 Processor Cores inside the ESP32 chip. I would like to get a diagram similar to the attached diagram (it is my idea) to see the sharing mechanism of ESP32's UART0 Port for onward connection to the OutputBox of the Arduino Serial Monitor.

Both cores are connected to the internal APB bus that goes to the UART. The APB bus makes sure register writes to the peripherals are serialized (as in: only one request can be sent over the bus at a time), but aside from that, both cores can happily access all UART registers at all times.

Does this APB (Advanced Peripheral Bus) contains --
Address Lines (how many -- 32?)
Data lines ? (how many -- 32?)
Read/write, IO-M Control lines?

It's a standard - you can read the spec here. In our case DATA_WIDTH is 32 bit, and I assume ADDR_WIDTH also is 32 bit.

Thanks! I am gaining slowly better insight about the architecture of LX6 Processor of the ESP32 system.

GolamMostafa wrote: ↑

Sun Jul 23, 2023 2:41 am

to see the sharing mechanism of ESP32's UART0 Port

It may or may not be relevant to you that the UART driver also uses synchronization primitives (semaphores/mutexes) in software to coordinate access to the peripheral between tasks.