VDD_SDIO when CHIP_PU low

[smantila]

Hi,

What happens to VDD_SDIO when CHIP_PU is pulled low?

We are planning to use ESP-WROOM-32 module and we would connect QSPI flash pins (GPIO6-11) from ESP module to main application processor for easy flash updating. Plan is to put CHIP_PU low so that ESP32 is not using flash and update QSPI flash with external SPI access. Problem is that VDD_SDIO is internal to module and it is connected to QSPI flash. Would our idea work or is VDD_SDIO shutdown when CHIP_PU is low?

[ESP_Angus]

Hi,

Sorry for the slow reply. I consulted with our hardware team who confirmed this should be fine. VDD_SDIO regulator is disabled when CHIP_PU (aka EN) is low and applying external voltage to the pin when the regulator is disabled is not a problem.

We recommend maintaining the normal VDD 3.3V input voltages to the ESP32 at this time, though (to avoid parasitic powering of the chip).

Angus

[taribo]

Hi ESP_Angus,

So you are saying that we should apply external (3.3V) voltage to VDD_SDIO pin of the ESP32 chip ?
But for the ESP-WROOM-32 module, this pin (VDD_SDIO) is not present externally. For ESP-WROOM-32 module, VDD_SDIO pin is only internally connected to flash chip. This connection is under the metallic RF shield.

So the question is: how can we power the flash of the ESP-WROOM-32 module, when we keep the ESP32 chip in power down (CHIP_PU low) ?