ESP32 Forum

Hello All,

I have designed a very smooth and low ripple 5V supply for my board. This gets coupled through a LDO 3.3V regulator to feed the ESP32 (same as most boards out there). When the ESP32 transmits WiFi, I see a 50-100mV drop in the 3.3V rail and it is being coupled through to the 5V side of the 3.3V reg.
Large electrolytic caps on the 5V side and the 3.3V side improved it greatly (to the 50-100mV measured result) but I would like to see further improvements.

Most 3.3V LDO regs all appear to have the same / similar load regulation characteristics so I am not yet convinced a change in reg will resolve the issue. Having a 16 bit ADC on board means I am very sensitive to voltage changes on the 5V rail.

Has anyone overcome this issue already?

Thanks
Jason

I am not yet convinced a change in reg will resolve the issue

It won't. Note that the 3.3V LDO does not "regulate" its input voltage. The drop you see on the 5V side is the result of the ESP drawing more current during TX and the 5V supply/rail failing to a) provide that amount of current while maintaining 5V, or b) react to the change in current quickly enough. There's nothing the LDO can do to change the current the load draws from the supply.

So some options are:
a) beef up the power supply
b) (further) reduce the impedance of the power supply (i.e. more caps), and make sure supply and ground/return lines and connections have low resistance
c) consider decoupling only the sensitive circuitry (ADC,...) from the 5V supply, which may be easier to achieve (less current) than stabilizing the whole 5V rail.