ESP32-S3 - how is the SRAM shared between the cores?

[Zoltan Janosy]

I did not find a definitive answer in the current documentation: how is simultaneous SRAM access by the two cores handled? Is the internal SRAM dual-ported (I mean that the two cores can address and access the same SRAM without additional wait states), or is there some kind of arbitration, making it slower to access the memory if both cores are running? Can the Permission Control (PMS) be used to grant exclusive access to one core, so that the two cores do not interfere?

[ESP_Sprite]

It's in the TRM:

The ROM as well as the SRAM are both clocked from CPU_CLK and can be accessed by the CPU in a single cycle.
The RTC FAST memory is clocked from the APB_CLOCK and the RTC SLOW memory from the FAST_CLOCK,
so access to these memories may be slower. DMA uses the APB_CLK to access memory.
Internally, the SRAM is organized in 32K-sized banks. Each CPU and DMA channel can simultaneously access
the SRAM at full speed, provided they access addresses in different memory banks.

From what I remember, when multiple masters try to access the same 32K bank, arbitration is round-robin.

[Zoltan Janosy]

Ahhh, I missed the “each CPU” part. Thank you for the clarification!