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HD signal on the SPI bus
Posted: Mon Apr 18, 2022 4:28 pm
by hpeteranvin
What is the function of the HD signal on the SPI bus? In particular, is there any way to use it for flow control purposes, such that the slave can indicate that it is not yet ready to return valid data and that the master (with ESP32-S2 as the master) will either not issue a clock pulse or ignore a clock pulse on which HD=? (0? 1?) is sampled?
Re: HD signal on the SPI bus
Posted: Tue Apr 19, 2022 3:27 am
by ESP_Sprite
HD is mostly a signal that is used in QSPI mode (where WP and HD of e.g. a flash chip are repurposed as D3/D4). I don't think the SPI peripheral can use it as an input aside from this purpose.
Re: HD signal on the SPI bus
Posted: Sat May 14, 2022 1:27 am
by hpeteranvin
Too bad. A flow control feature would be wonderful; unfortunately the board I'm working on doesn't have enough signals wired up to do QSPI (I'm doing DIO, though.)
What is really confusing to me is that HD appears to be an input in ESP32-x, but HOLD# is similarly an input on all flash chips I'm familiar with. So whatever function this pin has as an input in master mode is something totally different?
Re: HD signal on the SPI bus
Posted: Sat May 14, 2022 1:44 am
by ESP_Sprite
From what I recall, Hold on the ESP32 is a bidirectional pin. It's used as an input or output for QPI operations, and for non-QPI it gets assigned a static value.
Re: HD signal on the SPI bus
Posted: Sat May 14, 2022 1:48 am
by hpeteranvin
OK, that is *not* what the ESP32-S2 technical manual states.
Re: HD signal on the SPI bus
Posted: Sat May 14, 2022 6:08 am
by ESP_Sprite
Then either the TRM (or how it can be interpreted) or my recollection is wrong. Can you point to where it says HD is an input?