ESP32 Forum

I intend to use a ESP32-U4WDH as a controller for a custom RF module. We have laid out and built the first prototype board.
I can get communication to the CP2102N, but IDF.py does not connect. I see a signal going from the CP2102N to the ESP32 RX0 at the appropriate baud rate of 115200. I see unexplained transitions on the TX0 line. I am seeing a min pulse width of 500 uSec, which translated to about 2k baud. not 9600, not 14,400 not any reasonable baud rate. Incoming is 115.2

I should get JTAG connectivity tomorrow. I took a couple of these same chips and put them on a DevKitC Board without flash on the module and it connected immediately. I am seeing about a 20 mV signal form the clock at 40 MHz,
Any suggestions as to what else to look for would be appreciated.

Any chance you can post a schematic? Does manually resetting the chip (by pulling EN low momentarily) solve the issue?

I finally tried using idf.py monitor, without any flash load I am getting repeating messages of:


rst:0x10 (RTCWDT_RTC_RESET),boot:0x12 (SPI_FAST_FLASH_BOOT)
invalid header: 0xffffffff
invalid header: 0xffffffff
invalid header: 0xffffffff
invalid header: 0xffffffff
invalid header: 0xffffffff
invalid header: 0xffffffff
invalid header: 0xffffffff
invalid header: 0xffffffff
ets Jul 29 2019 12:21:46

rst:0x10 (RTCWDT_RTC_RESET),boot:0x12 (SPI_FAST_FLASH_BOOT)
invalid header: 0xffffffff
invalid header: 0xffffffff
invalid header: 0xffffffff
invalid header: 0xffffffff
invalid header: 0xffffffff
invalid header: 0xffffffff
invalid header: 0xffffffff
invalid header: 0xffffffff
ets Jul 29 2019 12:21:46

Previously, when I connected to the DevCKits with replaced processors, they connected and programmed immediately.
This is at 115,200 N81,

PS_USB Flash is a wireshark export of the first 400 messages or so out of about 8000 generated by a idf.py flash command.
I believe the ESP32 to be device 1.8.2, and the 2102 is device 1.8.0. PS_Txd_from... is a scope shot from the TXD pin on the 2102, which appears to be a good clean signal and pulse width of under 9 nSec.
I am showing a 40 MHz clock signal, at about 600 mV Please let me know if this is insufficient.

Scott.Bonomi wrote: ↑

Tue Aug 11, 2020 8:45 pm

I finally tried using idf.py monitor, without any flash load I am getting repeating messages of:

rst:0x10 (RTCWDT_RTC_RESET),boot:0x12 (SPI_FAST_FLASH_BOOT)
invalid header: 0xffffffff

This is what you would expect for a chip in "flash boot" mode when the flash has no contents(all 0xFF).

What do you see if you try to boot into download mode (GPIO0 low) while watching the serial output?

(BTW, the byte next to 'boot:' shows GPIO strapping pin values. 0x12 is GPIO0 & GPIO15 high.

You can also try running esptool.py with the "--trace" option, this will dump the serial interaction which can be easier to decipher than a USB capture in the CP2102N format.

Grounding GPIO0 and a reset does allow me to successfully connect by serial.
My current application, built from collecting pieces of several the examples to give me a starting point.
I am connecting to UART0 for PC communications.
Pin GPIO0 is floating, and at 3.3. Apparently we did not put the serial to reset logic on the first prototype board.
Am I correct in assuming that you reset the board every time you connect via USB Serial? The hard_reset arguments to esptool makes it look probable

Yes, this is correct.