ESP32 + LAN8720A: problem on boot, goes into download mode

[ha0x2328]

Hello,

I have an device with ESP32 and LAN8720A. It works fine, but sometimes after an power on reset the device is waiting for download instead boot normally. The GPIO0 has an pullup with 4.7K and is connected over 33R1% to PIN14 (INT/REFCLK0) on the LAN8720A. The oscillator output goes on the the same point between the pullup 4.7K and the 33R1%. The oscillator enable comes from ESP32 GPIO5 with pulldown 4.7K, wich only works after a normal reset.

So how does the ESP32 get into the wrong mode of operation?

Can I disable the "Waiting for download" mode via efuse? I can download everytime via OTA.

What can I do?

Best regards and Thank you

[deimos]

GPIO5 is propably not the best solution as it is driven high on bootup, which will enable the oscillator which possible pulls the GPIO0 low and enters the download mode.
So use a GPIO, which is not a strapping pin or do not use an oscillator at all and use the clock out mode on GPIO17 as clock for the LAN8720A.

[ha0x2328]

Thank you, do you have an working example schematic without external oscillator?

[deimos]

Thank you, do you have an working example schematic without external oscillator?

https://github.com/alexreinert/PCB/blob ... RF-ETH.pdf

[ha0x2328]

Your reply is very helpful. Thank you!

[giannifp]

Thanks for the design reference. I was also looking for options on how to connect this ETH_CLK for the LAN8270. I plan to use the ESP32-PICO which uses IO17 for internal Flash memory. There are no many other options available in which the ESP generates the clock with the CLK_OUT_180(O) signal. Question, can the IO0 be used as CLK_OUT(O) as indicated in the datasheet and invert the signal? How critical is propagation delay?

An option would be to have the external CLK and since the only input is IO0 then you would need some delay logic which disables the OSC and keeps the LAN8270 in reset while the system boots.

Thanks again and in advance!