ESP32 Forum

Hi,

is it possible to generate 12 MHz clock signal on some ESP32-WROOM32 pin (to be used as square clock for external component) ?

The duty resolution can be lowered down to 1 bit in which case the maximum frequency is 40 MHz, but only the duty of 50% is available

Which looks good, means that I can generate frequency up to 40 MHz, however 40MHz/12MHz = 3.33333 which is not a good divisor at all, in other words I need to change timer clock to something more useful for me (e.g. 48 MHz).

Or maybe can I use some other ESP32 peripheral such as SPI or I2S to generate continuous stream of data 000 111 000 etc ?

Thanks!

mhi32768 wrote: ↑

Wed Jan 15, 2020 8:27 am

Hi,
is it possible to generate 12 MHz clock signal on some ESP32-WROOM32 pin (to be used as square clock for external component) ?

hi
one possible way is , you can try APLL to generate a constant clock on a pin. look at 3.2.7 Audio PLL (s. 42 ) in the TRM
you find more detailed things in the TRM ( technical reference manual ) of the ESP32, which is attached and you can get from espressif's documents share in en and in cn.

example play with registers or/and function

hope this helps for the start.

best wishes
rudi

also you can try this with little edit work to your wished 12MHz and other GPIO:
example how to generate 20MHz square wave at 50% duty on GPIO18.

best wishes
rudi

Thanks, which pin function is then used to output the 12 MHz clock signal to GPIO (TRM chapter 4.9 table ) ? For the first (ADC clk) solution. I am not very familiar with I2S..

About LEDC/PWM, I am not sure but I think frequency cannot be easily changed (base 80MHz) ? And 80 MHz is not very good for generating 12 MHz by single divisor.

Sorry for long time no try, I had another important work to do. I tried LEDC 12MHz clock generating approach an it works, somehow it can set the clock, BUT if I measure it on oscilloscope I get clock signal ranging from 11.4 to 13.3 MHz. This is unusable ...

Maybe it can be useful.
Many resources in only small chip - awesome!

I2S0 Clock (master clock) up to 80MHz derived from APLL clock
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