I have a design based around ESP32-PICO-D4 and going for certification soon. Now I want to run ESP32_RF_TEST_BIN_V1.5.0_20190812.bin on our hardware but I'm unable to get it to boot properly.
To be sure that there are no problems with the hardware I also tried on the ESP32-PICO-KIT and ESP32-WROOM-32.
ESP32-WROOM-32 runs the binary successfully but I'm unable to get it to start on ESP32-PICO-KIT.
I get same error message on ESP32-PICO-KIT and my custom hardware based around ESP32-PICO-D4.
How are you supposed to program this binary to the PICO-D4 to get it to run properly? I'm using espRFTool_2.0.exe available from https://www.espressif.com/en/support/download/overview
ESP-WROOM-32 output:
sync...
sync success
esp_mac:cc-50-e3-92-a9-6c
load start
open serial fail...
Hash of data verified.
load to flash success
load bin success
start rf test
SET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 0, SPIWP:0x00
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:QIO, clock div:2
load:0x40080000,len:149712
1162 mmu set 00010000, pos 00010000
1162 mmu set 00020000, pos 00020000
load:0x3ffc4000,len:2668
load:0x3ffc4a6c,len:28580
entry 0x40080058
bss start 0x3ffcba10 end 0x3ffd9af8
init bss 0
rtc v240 Jan 2 2019 16:22:15
xtal clk=40, CRYSTAL_SELECT=0
efuse_MAC: 0x4bcc50-e392a96c
phy_version: 4150, 99b5c0a, Aug 12 2019, 14:12:06, 0, 2
*RFTestBIN 150
wait:
ESP32-PICO-KIT log output:
sync...
sync success
esp_mac:d8-a0-1d-69-f6-74
load start
open serial fail...
Hash of data verified.
load to flash success
load bin success
start rf test
FLASH_BOOT)
configsip: 188777542, SPIWP:0x00
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:QIO, clock div:2
load:0x40080000,len:149712
1162 mmu set 00010000, pos 00010000
1162 mmu set 00020000, pos 00020000
load:0xffffffff,len:-1
ets Jun 8 2016 00:22:57
rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 188777542, SPIWP:0x00
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:QIO, clock div:2
load:0x40080000,len:149712
1162 mmu set 00010000, pos 00010000
1162 mmu set 00020000, pos 00020000
load:0xffffffff,len:-1
ets Jun 8 2016 00:22:57
rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 188777542, SPIWP:0x00
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:QIO, clock div:2
load:0x40080000,len:149712
1162 mmu set 00010000, pos 00010000
1162 mmu set 00020000, pos 00020000
load:0xffffffff,len:-1
ets Jun 8 2016 00:22:57
rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 188777542, SPIWP:0x00
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:QIO, clock div:2
load:0x40080000,len:149712
1162 mmu set 00010000, pos 00010000
1162 mmu set 00020000, pos 00020000
load:0xffffffff,len:-1
ets Jun 8 2016 00:22:57
rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 188777542, SPIWP:0x00
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:QIO, clock div:2
load:0x40080000,len:149712
1162 mmu set 00010000, pos 00010000
1162 mmu set 00020000, pos 00020000
load:0xffffffff,len:-1
ets Jun 8 2016 00:22:57
rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 188777542, SPIWP:0x00
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:QIO, clock div:2
load:0x40080000,len:149712
1162 mmu set 00010000, pos 00010000
1162 mmu set 00020000, pos 00020000
load:0xffffffff,len:-1
ets Jun 8 2016 00:22:57
rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 188777542, SPIWP:0x00
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:QIO, clock div:2
load:0x40080000,len:149712
1162 mmu set 00010000, pos 00010000
1162 mmu set 00020000, pos 00020000
load:0xffffffff,len:-1
ets Jun 8 2016 00:22:57
rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 188777542, SPIWP:0x00
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:QIO, clock div:2
load:0x40080000,len:149712
1162 mmu set 00010000, pos 00010000
1162 mmu set 00020000, pos 00020000
load:0xffffffff,len:-1
ets Jun 8 2016 00:22:57
rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 188777542, SPIWP:0x00
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:QIO, clock div:2
load:0x40080000,len:149712
1162 mmu set 00010000, pos 00010000
1162 mmu set 00020000, pos 00020000
load:0xffffffff,len:-1
ets Jun 8 2016 00:22:57
rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 188777542, SPIWP:0x00
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:QIO, clock div:2
load:0x40080000,len:149712
1162 mmu set 00010000, pos 00010000
1162 mmu set 00020000, pos 00020000
load:0xffffffff,len:-1
ets Jun 8 2016 00:22:57
rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 188777542, SPIWP:0x00
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:QIO, clock div:2
load:0x40080000,len:149712
1162 mmu set 00010000, pos 00010000
1162 mmu set 00020000, pos 00020000
load:0xffffffff,len:-1
ets Jun 8 2016 00:22:57
rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 188777542, SPIWP:0x00
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:QIO, clock div:2
load:0x40080000,len:149712
1162 mmu set 00010000, pos 00010000
1162 mmu set 00020000, pos 00020000
load:0xffffffff,len:-1
ets Jun 8 2016 00:22:57
rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 188777542, SPIWP:0x00
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:QIO, clock div:2
load:0x40080000,len:149712
1162 mmu set 00010000, pos 00010000
1162 mmu set 00020000, pos 00020000
load:0xffffffff,len:-1
ets Jun 8 2016 00:22:57
rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 188777542, SPIWP:0x00
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:QIO, clock div:2
load:0x40080000,len:149712
1162 mmu set 00010000, pos 00010000
1162 mmu set 00020000, pos 00020000
load:0xffffffff,len:-1
ets Jun 8 2016 00:22:57
rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 188777542, SPIWP:0x00
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:QIO, clock div:2
load:0x40080000,len:149712
1162 mmu set 00010000, pos 00010000
1162 mmu set 00020000, pos 00020000
load:0xffffffff,len:-1
ets Jun 8 2016 00:22:57
rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 188777542, SPIWP:0x00
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:QIO, clock div:2
load:0x40080000,len:149712
1162 mmu set 00010000, pos 00010000
1162 mmu set 00020000, pos 00020000
load:0xffffffff,len:-1
ets Jun 8 2016 00:22:57
rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 188777542, SPIWP:0x00
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:QIO, clock div:2
load:0x40080000,len:149712
1162 mmu set 00010000, pos 00010000
1162 mmu set 00020000, pos 00020000
load:0xffffffff,len:-1
ets Jun 8 2016 00:22:57
rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 188777542, SPIWP:0x00
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:QIO, clock div:2
load:0x40080000,len:149712
1162 mmu set 00010000, pos 00010000
1162 mmu set 00020000, pos 00020000
load:0xffffffff,len:-1
ets Jun 8 2016 00:22:57
rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 188777542, SPIWP:0x00
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:QIO, clock div:2
load:0x40080000,len:149712
1162 mmu set 00010000, pos 00010000
1162 mmu set 00020000, pos 00020000
load:0xffffffff,len:-1
ets Jun 8 2016 00:22:57
rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 188777542, SPIWP:0x00
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:QIO, clock div:2
load:0x40080000,len:149712
1162 mmu set 00010000, pos 00010000
1162 mmu set 00020000, pos 00020000
load:0xffffffff,len:-1
ets Jun 8 2016 00:22:57
rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 188777542, SPIWP:0x00
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:QIO, clock div:2
load:0x40080000,len:149712
1162 mmu set 00010000, pos 00010000
1162 mmu set 00020000, pos 00020000
load:0xffffffff,len:-1