Unable to run ESP32_RF_TEST_BIN on PICO-D4

[rajtantajtan]

Hi,

I have a design based around ESP32-PICO-D4 and going for certification soon. Now I want to run ESP32_RF_TEST_BIN_V1.5.0_20190812.bin on our hardware but I'm unable to get it to boot properly.

To be sure that there are no problems with the hardware I also tried on the ESP32-PICO-KIT and ESP32-WROOM-32.

ESP32-WROOM-32 runs the binary successfully but I'm unable to get it to start on ESP32-PICO-KIT.

I get same error message on ESP32-PICO-KIT and my custom hardware based around ESP32-PICO-D4.

How are you supposed to program this binary to the PICO-D4 to get it to run properly? I'm using espRFTool_2.0.exe available from https://www.espressif.com/en/support/download/overview

ESP-WROOM-32 output:

sync...
sync success
esp_mac:cc-50-e3-92-a9-6c
load start
open serial fail...
Hash of data verified.
load to flash success
load bin success
start rf test
SET),boot:0x13 (SPI_FAST_FLASH_BOOT)

configsip: 0, SPIWP:0x00

clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00

mode:QIO, clock div:2

load:0x40080000,len:149712

1162 mmu set 00010000, pos 00010000

1162 mmu set 00020000, pos 00020000

load:0x3ffc4000,len:2668

load:0x3ffc4a6c,len:28580

entry 0x40080058

bss start 0x3ffcba10 end 0x3ffd9af8

init bss 0

rtc v240 Jan 2 2019 16:22:15

xtal clk=40, CRYSTAL_SELECT=0

efuse_MAC: 0x4bcc50-e392a96c

phy_version: 4150, 99b5c0a, Aug 12 2019, 14:12:06, 0, 2

*RFTestBIN 150

wait:

ESP32-PICO-KIT log output:

sync...
sync success
esp_mac:d8-a0-1d-69-f6-74
load start
open serial fail...
Hash of data verified.
load to flash success
load bin success
start rf test
FLASH_BOOT)

configsip: 188777542, SPIWP:0x00

clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00

mode:QIO, clock div:2

load:0x40080000,len:149712

1162 mmu set 00010000, pos 00010000

1162 mmu set 00020000, pos 00020000

load:0xffffffff,len:-1

ets Jun 8 2016 00:22:57



rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)

configsip: 188777542, SPIWP:0x00

clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00

mode:QIO, clock div:2

load:0x40080000,len:149712

1162 mmu set 00010000, pos 00010000

1162 mmu set 00020000, pos 00020000

load:0xffffffff,len:-1

ets Jun 8 2016 00:22:57



rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)

configsip: 188777542, SPIWP:0x00

clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00

mode:QIO, clock div:2

load:0x40080000,len:149712

1162 mmu set 00010000, pos 00010000

1162 mmu set 00020000, pos 00020000

load:0xffffffff,len:-1

ets Jun 8 2016 00:22:57



rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)

configsip: 188777542, SPIWP:0x00

clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00

mode:QIO, clock div:2

load:0x40080000,len:149712

1162 mmu set 00010000, pos 00010000

1162 mmu set 00020000, pos 00020000

load:0xffffffff,len:-1

ets Jun 8 2016 00:22:57



rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)

configsip: 188777542, SPIWP:0x00

clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00

mode:QIO, clock div:2

load:0x40080000,len:149712

1162 mmu set 00010000, pos 00010000

1162 mmu set 00020000, pos 00020000

load:0xffffffff,len:-1

ets Jun 8 2016 00:22:57



rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)

configsip: 188777542, SPIWP:0x00

clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00

mode:QIO, clock div:2

load:0x40080000,len:149712

1162 mmu set 00010000, pos 00010000

1162 mmu set 00020000, pos 00020000

load:0xffffffff,len:-1

ets Jun 8 2016 00:22:57



rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)

configsip: 188777542, SPIWP:0x00

clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00

mode:QIO, clock div:2

load:0x40080000,len:149712

1162 mmu set 00010000, pos 00010000

1162 mmu set 00020000, pos 00020000

load:0xffffffff,len:-1

ets Jun 8 2016 00:22:57



rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)

configsip: 188777542, SPIWP:0x00

clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00

mode:QIO, clock div:2

load:0x40080000,len:149712

1162 mmu set 00010000, pos 00010000

1162 mmu set 00020000, pos 00020000

load:0xffffffff,len:-1

ets Jun 8 2016 00:22:57



rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)

configsip: 188777542, SPIWP:0x00

clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00

mode:QIO, clock div:2

load:0x40080000,len:149712

1162 mmu set 00010000, pos 00010000

1162 mmu set 00020000, pos 00020000

load:0xffffffff,len:-1

ets Jun 8 2016 00:22:57



rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)

configsip: 188777542, SPIWP:0x00

clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00

mode:QIO, clock div:2

load:0x40080000,len:149712

1162 mmu set 00010000, pos 00010000

1162 mmu set 00020000, pos 00020000

load:0xffffffff,len:-1

ets Jun 8 2016 00:22:57



rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)

configsip: 188777542, SPIWP:0x00

clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00

mode:QIO, clock div:2

load:0x40080000,len:149712

1162 mmu set 00010000, pos 00010000

1162 mmu set 00020000, pos 00020000

load:0xffffffff,len:-1

ets Jun 8 2016 00:22:57



rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)

configsip: 188777542, SPIWP:0x00

clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00

mode:QIO, clock div:2

load:0x40080000,len:149712

1162 mmu set 00010000, pos 00010000

1162 mmu set 00020000, pos 00020000

load:0xffffffff,len:-1

ets Jun 8 2016 00:22:57



rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)

configsip: 188777542, SPIWP:0x00

clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00

mode:QIO, clock div:2

load:0x40080000,len:149712

1162 mmu set 00010000, pos 00010000

1162 mmu set 00020000, pos 00020000

load:0xffffffff,len:-1

ets Jun 8 2016 00:22:57



rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)

configsip: 188777542, SPIWP:0x00

clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00

mode:QIO, clock div:2

load:0x40080000,len:149712

1162 mmu set 00010000, pos 00010000

1162 mmu set 00020000, pos 00020000

load:0xffffffff,len:-1

ets Jun 8 2016 00:22:57



rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)

configsip: 188777542, SPIWP:0x00

clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00

mode:QIO, clock div:2

load:0x40080000,len:149712

1162 mmu set 00010000, pos 00010000

1162 mmu set 00020000, pos 00020000

load:0xffffffff,len:-1

ets Jun 8 2016 00:22:57



rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)

configsip: 188777542, SPIWP:0x00

clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00

mode:QIO, clock div:2

load:0x40080000,len:149712

1162 mmu set 00010000, pos 00010000

1162 mmu set 00020000, pos 00020000

load:0xffffffff,len:-1

ets Jun 8 2016 00:22:57



rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)

configsip: 188777542, SPIWP:0x00

clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00

mode:QIO, clock div:2

load:0x40080000,len:149712

1162 mmu set 00010000, pos 00010000

1162 mmu set 00020000, pos 00020000

load:0xffffffff,len:-1

ets Jun 8 2016 00:22:57



rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)

configsip: 188777542, SPIWP:0x00

clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00

mode:QIO, clock div:2

load:0x40080000,len:149712

1162 mmu set 00010000, pos 00010000

1162 mmu set 00020000, pos 00020000

load:0xffffffff,len:-1

ets Jun 8 2016 00:22:57



rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)

configsip: 188777542, SPIWP:0x00

clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00

mode:QIO, clock div:2

load:0x40080000,len:149712

1162 mmu set 00010000, pos 00010000

1162 mmu set 00020000, pos 00020000

load:0xffffffff,len:-1

ets Jun 8 2016 00:22:57



rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)

configsip: 188777542, SPIWP:0x00

clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00

mode:QIO, clock div:2

load:0x40080000,len:149712

1162 mmu set 00010000, pos 00010000

1162 mmu set 00020000, pos 00020000

load:0xffffffff,len:-1

ets Jun 8 2016 00:22:57



rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)

configsip: 188777542, SPIWP:0x00

clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00

mode:QIO, clock div:2

load:0x40080000,len:149712

1162 mmu set 00010000, pos 00010000

1162 mmu set 00020000, pos 00020000

load:0xffffffff,len:-1

[yamosw]

Hi rajtantajtan -

Looking at the log, it seems that it is rebooting without successfully communicating with FlashROM.

ESP32 looks at the Firmware header and sets the SPI for external FlashROM (PICO-D4 external FlashROM is in the chip package).

Looking at the header in ESP32_RF_TEST_BIN_V1.5.0_20190812.bin, spi_mode = ESP_IMAGE_SPI_MODE_QIO(0x00), spi_size = ESP_IMAGE_FLASH_SIZE_1MB(0x0), spi_speed = ESP_IMAGE_SPI_SPEED_40M(0x0).

ESP32_RF_TEST_BIN_V1.5.0_20190812.bin header.png (6.91 KiB) Viewed 2744 times

Firmware headers are stored in the esp_image_header_t structure in order from the top.
That is, the first “0xE9” is magic, “0x03” is segment_count, and “0x00” is spi_mode. (Note: be careful to endian)

Change spi_mode, spi_size, and spi_speed as shown in the screenshot below.
spi_mode = ESP_IMAGE_SPI_MODE_DIO(0x02), spi_size = ESP_IMAGE_FLASH_SIZE_4MB(0x2), spi_speed = ESP_IMAGE_SPI_SPEED_80M(0xF).

ESP32_RF_TEST_BIN_V1.5.0_20190812.bin header modified.png (7.04 KiB) Viewed 2744 times

Try writing it after modifying the binary.
When writing ESP32_RF_TEST_BIN_V1.5.0_20190812.bin by manually specifying the offset address, set offset to 0x1000.

I saw that PICO-D4 works now.

reference: "~\esp-idf\components\bootloader_support\include\esp_image_format.h"

Code: [Select all] [Expand/Collapse]

1. typedef enum {
2.     ESP_IMAGE_SPI_MODE_QIO,
3.     ESP_IMAGE_SPI_MODE_QOUT,
4.     ESP_IMAGE_SPI_MODE_DIO,
5.     ESP_IMAGE_SPI_MODE_DOUT,
6.     ESP_IMAGE_SPI_MODE_FAST_READ,
7.     ESP_IMAGE_SPI_MODE_SLOW_READ
8. } esp_image_spi_mode_t;
9. /* SPI flash clock frequency */
10. typedef enum {
11.     ESP_IMAGE_SPI_SPEED_40M,
12.     ESP_IMAGE_SPI_SPEED_26M,
13.     ESP_IMAGE_SPI_SPEED_20M,
14.     ESP_IMAGE_SPI_SPEED_80M = 0xF
15. } esp_image_spi_freq_t;
16. /* Supported SPI flash sizes */
17. typedef enum {
18.     ESP_IMAGE_FLASH_SIZE_1MB = 0,
19.     ESP_IMAGE_FLASH_SIZE_2MB,
20.     ESP_IMAGE_FLASH_SIZE_4MB,
21.     ESP_IMAGE_FLASH_SIZE_8MB,
22.     ESP_IMAGE_FLASH_SIZE_16MB,
23.     ESP_IMAGE_FLASH_SIZE_MAX
24. } esp_image_flash_size_t;
25. #define ESP_IMAGE_HEADER_MAGIC 0xE9
26. /* Main header of binary image */
27. typedef struct {
28.     uint8_t magic;
29.     uint8_t segment_count;
30.     /* flash read mode (esp_image_spi_mode_t as uint8_t) */
31.     uint8_t spi_mode;
32.     /* flash frequency (esp_image_spi_freq_t as uint8_t) */
33.     uint8_t spi_speed: 4;
34.     /* flash chip size (esp_image_flash_size_t as uint8_t) */
35.     uint8_t spi_size: 4;
36.     uint32_t entry_addr;
37.     /* WP pin when SPI pins set via efuse (read by ROM bootloader, the IDF bootloader uses software to configure the WP
38.      * pin and sets this field to 0xEE=disabled) */
39.     uint8_t wp_pin;
40.     /* Drive settings for the SPI flash pins (read by ROM bootloader) */
41.     uint8_t spi_pin_drv[3];
42.     /* Reserved bytes in ESP32 additional header space, currently unused */
43.     uint8_t reserved[11];
44.     /* If 1, a SHA256 digest "simple hash" (of the entire image) is appended after the checksum. Included in image length. This digest
45.      * is separate to secure boot and only used for detecting corruption. For secure boot signed images, the signature
46.      * is appended after this (and the simple hash is included in the signed data). */
47.     uint8_t hash_appended;
48. } __attribute__((packed))  esp_image_header_t;

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