ESP32 Forum

Ian777 wrote: ↑

Fri Apr 26, 2019 2:58 pm

Hey everyone,

I've got my SPI init code defined as the following:

Code: Select all

#define GPIO_MOSI 21
#define GPIO_MISO 14
#define GPIO_SCLK 12
#define GPIO_CS 22

    ESP_LOGI(TAG1,"Started master SPI");
    esp_err_t ret;
    spi_device_handle_t handle;

    //Configuration for the SPI bus
    spi_bus_config_t buscfg={
        .mosi_io_num=GPIO_MOSI,
        .miso_io_num=GPIO_MISO,
        .sclk_io_num=GPIO_SCLK,
        .quadwp_io_num=-1,
        .quadhd_io_num=-1
    };
    spi_device_interface_config_t devcfg={
        .command_bits=0,
        .address_bits=0,
        .dummy_bits=0,
        .clock_speed_hz=5000000,
        .duty_cycle_pos=128,        //50% duty cycle
        .mode=0,
        .spics_io_num=GPIO_CS,
        .cs_ena_posttrans=3,        //Keep the CS low 3 cycles after transaction, to stop slave from missing the last bit when CS has less propagation delay than CLK
        .queue_size=3
};

Is there anyway to set the CS pin mode as a pull down as I have an external pullup resistor on the line?

Thanks in advance for any help!

Ritesh wrote: ↑

Sun Apr 28, 2019 9:49 am

Ian777 wrote: ↑

Fri Apr 26, 2019 2:58 pm

Hey everyone,

I've got my SPI init code defined as the following:

Code: Select all

#define GPIO_MOSI 21
#define GPIO_MISO 14
#define GPIO_SCLK 12
#define GPIO_CS 22

    ESP_LOGI(TAG1,"Started master SPI");
    esp_err_t ret;
    spi_device_handle_t handle;

    //Configuration for the SPI bus
    spi_bus_config_t buscfg={
        .mosi_io_num=GPIO_MOSI,
        .miso_io_num=GPIO_MISO,
        .sclk_io_num=GPIO_SCLK,
        .quadwp_io_num=-1,
        .quadhd_io_num=-1
    };
    spi_device_interface_config_t devcfg={
        .command_bits=0,
        .address_bits=0,
        .dummy_bits=0,
        .clock_speed_hz=5000000,
        .duty_cycle_pos=128,        //50% duty cycle
        .mode=0,
        .spics_io_num=GPIO_CS,
        .cs_ena_posttrans=3,        //Keep the CS low 3 cycles after transaction, to stop slave from missing the last bit when CS has less propagation delay than CLK
        .queue_size=3
};

Is there anyway to set the CS pin mode as a pull down as I have an external pullup resistor on the line?

Thanks in advance for any help!

I think there is no any way to make it pull down as you have already connected pull up resistor. But still try with making gpio configuration as pull down but I am sure it won't work as you required.

Still, Can you please question into hardware section then might be you will get proper solution for same.