RFE/suggestion: minor changes to SPI to support JTAG master operation

[hpeteranvin]

Hi,

I have somewhat successfully used the ESP32-S2 SPI unit as a JTAG master, but it has several issues that unfortunately require falling back to bitbanging several operations. JTAG is very closely related to SPI, but it has a couple of key differences which cause trouble.

The signal mapping is basically: TDI = MOSI, TDO = MISO, TCK = SCLK, TMS = CS# (but see below); TRST if present can be connected to a GPIO.

1. On a read operation, the data in fractional bytes are lost. JTAG requires the ability to read and write transactions of any length, and working around it by issuing extra clocks (TCK) is not acceptable.

2. JTAG TMS is fairly similar to SPI CS#, with the key difference that TMS needs to go high one cycle *before* the end of the transaction, that is, the last TCK positive edge of the transaction is issued with TMS high, when existing the all important SHIFT_DR and SHIFT_IR states. This is unlike SPI where CS# goes high *after* the last bit has been clocked. This kind of "negative CS# delay" would be great to support, in order to add a redundant single-bit transaction. This is the only case in JTAG when both TMS and TDI (and TDO) carry information at the same time; an unfortunate design decision.

3. For state transitions, a bit pattern of up to 5 bits needs to be issued on the TMS pin (including the transition mentioned under #2). Although this is generally not a big deal to bit bang, doing so in an interrupt handler is needlessly costly; also, a handful of devices are known to be timing-sensitive for this operation and not appreciating a major change to the TCK frequency (in violation of spec.) It can also be done by switching MOSI to TMS using the GPIO matrix, but that is (a) kind of slow, (b) not [currently] possible to background using segmented DMA. If there was a way to do this using segmented DMA it would allow an arbitrary number of transactions to be issued at once. As the number of bits is small, this should, if necessary, be fine to do with multiple transactions (with CS# in the chosen state, cycle TCK with either a fixed TDI or the final TDI from the last transaction); however, it would obviously be better if this was not necessary and could be done programmatically.

One option for handling both #2 and #3 as well as the existing CS# postdelay features would be to have a short (≥ 5 bit) shift register to select the CS# pin output pattern for each cycle starting with the final data bit cycle (but not the internal CS# state), and extending the SPI_CLK_MODE to 3 bits wide. For normal SPI this register would then contain 0111... in wire order. The best for performance would be if this was a field in SPI_CTRL1_REG to allow the bit sequence and SPI_CLK_MODE = the length of the sequence to be written together.

4. Some devices (probably not many) require that TDO (MISO) is forwarded to TDI (MOSI) with a delay of one clock cycle. This I would consider entirely optional.

[ESP_Sprite]

These are good suggestions. We also have a project ourselves that does JTAG, that may also profit from this. I'll go and see if these issues are work-around-able somehow, and if not, I'll create an internal ticket for the digital team. I unfortunately can't tell you when it'll be looked at, let alone when any silicon may have an improved SPI peripheral; unfortunately new chip releases take a while.