Here's an illustration of the problem:
- Screenshot_20201029_020541.png (57.85 KiB) Viewed 1695 times
Any ideas what's happening here? A higher priority interrupt maybe? How to raise the SPI peripheral's interrupts' priority? Thanks!
Interrupts from SPI master delayed
Interrupts from SPI master delayed
I have an application where I need to trigger short SPI transfers quite often (at around a rate of 13000 Hz) and on time. But a few times every second I'm unable to meet the deadline because something is blocking hardware interrupts from the peripheral.
Here's an illustration of the problem:
D1 is the SPI clock, D2 is a GPIO that I set high in the post-transaction callback and set low in the pre-transaction callback. The post-transaction call back also kicks off the next SPI transfer. As you can see, there's a more than 500 us gap when no transaction is running because it is not kicked off in time from the pre callback because it's delayed. I also observed some delays of 100-160 us.
Any ideas what's happening here? A higher priority interrupt maybe? How to raise the SPI peripheral's interrupts' priority? Thanks!
Here's an illustration of the problem:
D1 is the SPI clock, D2 is a GPIO that I set high in the post-transaction callback and set low in the pre-transaction callback. The post-transaction call back also kicks off the next SPI transfer. As you can see, there's a more than 500 us gap when no transaction is running because it is not kicked off in time from the pre callback because it's delayed. I also observed some delays of 100-160 us.
Any ideas what's happening here? A higher priority interrupt maybe? How to raise the SPI peripheral's interrupts' priority? Thanks!
Who is online
Users browsing this forum: Zipdox and 162 guests