So, I did read some more discussions and threads, and understand a bit more about the current bursts that occur during certain events (ie wi-fi things and flash operations), so maybe there is indeed a vdd rail lag in my test setup when it was in this 'failing' state..30AWG is something like 320milliohms/m resistance, so even a fairly short length of wire has significant resistance compared to a small ceramic cap's ESR (remember the effective length is doubled due to power/ground both being wired this way). I would bet money this is why the ESP32 is randomly failing during flash operations (which require small bursts of power consumption), and adding the transistor-driven input to EN inadvertently improves the power supply by connecting a second parasitic power wire via the EN pin
So if we go with this theory...in my setup with the transistor, the second 'wire' from 3.3V vdd is only going to the npn collector...the GPIO is going to the base through a 1k resistor...
I'm not sure i see how the esp32 Vdd could see this setup as a parasitic voltage source? Unless you are saying 'internally' in the ESP32 core it is able to pull current through the EN pin?
Do you know exactly how the logic is designed internally in the ESP32 core, is 'CHIP_PU' just a single connection to the internal LDO 'enable' pin, and that's it?
Also, don't forget, one of the tests I did, when it was in this failing state, was I shorted (right on the ESP32 pads), Vdd to EN.. and the failures went away (this was when En was still just pulled up via 10k res)...