i2s lcd mode data out idle state level

[Baldhead]

Hi,

I would like to know what are the idle state level of i2s data output, after data send out ?
Example: 8 data outputs.

All output pins are all at high logic level or all output pins at low logic level ?

Or the output pins store last byte transmitted state ?

Or the output pins are all in tristate(high impedance) ?

Thank's.

[Baldhead]

no one ?

[Baldhead]

??????

[Baldhead]

By my tests the output goes back to idle state after a little time.

[Baldhead]

Hi,

With 10 MHz using APLL_CLK the data bus stay active(i am testing with logic level = 1) for 500 ns( 5 clock period ) after last clock(ws pin) rising edge, and after this 500ns time the i2s module stay in idle state and the port stay in tristate i think(even though the data bus gets 0 volts, maybe i2s force the data bus to zero volts).

[ESP_houwenxiang]

Hi, Baldhead

the data out idle state level is 0, when the data, when the data transmission is complete and reset tx mode(tx_reset = 1; tx_reset = 0;), the data line will return to 0.

[Baldhead]

Hi,

I put a delay before i call the "instruction" "tx_reset( )" to take a test like:

"send Data";
while ( ! ( I2SX.state.tx_idle ) );
vTaskDelay(1/portTICK_PERIOD_MS); // 1 milisecond.
tx_reset( );

Code: Select all

static void tx_reset( )
{
    I2SX.conf.tx_reset = 1;    // Set this bit to reset the transmitter. (R/W)
    I2SX.conf.tx_reset = 0;
}

The i2s parallel output now it took 90 us( 90 clock periods with 10 MHz) to enter in "idle state" ( timeout maybe ? ).


The time that i2s bus stay active after last rising edge of the clock are configurable ?

If time could be "infinite" i could test with leds on parallel port to verify that data is being sent correctly in the absence of a logical analyzer.


Thank's.