Hard-reset not working

[tatulea]

Hi,

I have a custom board with a ESP-WROVER-B. There is a CP2102N that has the reset and boot circuit implemented as it is in the ESP-DevkitC schematic (RTS, DTR, two transistors, EN and IO0).

The first problem that I had was the fact that my board was not getting into "download mode" in order to flash it. For now, it looks like this was solved by adding a capacitor between EN and GND. After this, the flashing is working, but the hard-reset is not. I had a look here (https://github.com/espressif/esptool/issues/399) and I added time.sleep(2). It looks like it's working.

My CP2102N is A01 revision and it seems to be a hardware problem and because of this the hard-reset is not working.
I also have an ESP-DevKitC which has the same A01 revision and the v4 schematic of it uses A01 as well. The question is, why the hard-reset is working with A01 on DevKitC, but not on my board?

[Nikonov_94]

Oh, that's great you asked, I was in the process of ordering an A01 revision CP2102N bridge... Is this issue recurrent with all of these models, and if yes, can it be solved? If no, what would be a good alternative?

[captain_morgan]

I'm using this part successfully in several of my designs. First thing I notice in your description is your reset circuit, typically this is implemented with two transistors and two resistors. Here's one of my recent schematics https://cdn.hackaday.io/files/163861701 ... coffin.pdf. Additionally you mention the cap on EN, do you have a pull-up resistor on EN also? I found missing this caused really inconsistent flashing in an early design.

If these don't help you should post the schematic of your CP2102 circuit for further help. But other things to check...
What's the voltage on VDDIO?
VBUS connected? (Ignore my voltage divider, turned out unneeded)
RSTb pulled high? (specifically to VDDIO)

[ESP_Angus]

hard-reset is not. I had a look here (https://github.com/espressif/esptool/issues/399) and I added time.sleep(2). It looks like it's working.

If the sleep here fixes the problem, and you need to power cycle the CP2102N to get it back otherwise, then it almost certainly is this hardware issue. Driver updates have been released for macOS and Windows to fix this, but Linux still does not have one - so the only known fix on Linux is to update to A02 silicon or downgrade to a CP2102 chip.

If you're using one of the other OSes, try updating your drivers.

[captain_morgan]

Interesting.... and maybe a bit concerning? I'm using the CP2102N-A01 and have no issue flashing from several different Linux machines. Do you have any further reading on this issue?

[ESP_Angus]

The github issue link above has a fairly good summary of my understanding of the problem, and a link to a SiLabs forum post reporting the problem.

[tatulea]

First thing I notice in your description is your reset circuit, typically this is implemented with two transistors and two resistors

This is my reset circuit:

rst.PNG (13.16 KiB) Viewed 15353 times

Additionally you mention the cap on EN, do you have a pull-up resistor on EN also? I found missing this caused really inconsistent flashing in an early design.

For now, I just have a pull-up resistor (10k) on EN, without any capacitor. This way, it is not working and I placed a capacitor by hand and it's working this way. I can see that you don't have any capacitor on EN. Is it working like that?

If these don't help you should post the schematic of your CP2102 circuit for further help. But other things to check...
What's the voltage on VDDIO?
VBUS connected? (Ignore my voltage divider, turned out unneeded)
RSTb pulled high? (specifically to VDDIO)

My VIO is not connected to anything.
The VDD from CP2102 is connected to the same VDD as ESP32. Should it be connected or not? I can see that it is not in your schematic.

rst.PNG (13.16 KiB) Viewed 15353 times

[captain_morgan]

First and foremost from your original post, you should check the date code on your device to see if it does in fact have this hardware issue. After 1639 the issue has been fixed.
https://www.silabs.com/documents/public ... Update.pdf


...back to debugging...

I have never included a capacitor on EN and it works just fine.

In the design I showed, the CP2102N is in Bus-Powered mode, meaning the chip is powered from the USB and saves power when using battery. With this setup, you apply 5V to VREGIN and VDD becomes a 3.3V OUTPUT, that is fed back into VIO, which is the supply voltage for all RX, TX, DTR, RTS, etc.

From the datasheet pin description, Table 5.2

VDD: Supply Power Input / 5V Regulator Output

Since you have VBUS connected to VREGIN, you're actually outputting 3.3v back into your VDD net! I'm a bit surprised nothing has given up the smoke.

Additionally without any power going into VIO, I suspect you are getting low if any voltage out on all your IO pins. Again from the pin description table.

VIO: I/O Supply Power Input

My best guess at this point is you're half running in bus-powered and half external powered. You need to either disconnect VDD or connect VREGIN to VDD instead of VBUS. These are described in Figure 2.1, 2.2, 2.3
In either case I think you need the VDD pin and VIO pin connected.

Hopefully this helps you progress, I struggled with this chip as well, and personally don't think the datasheet is very clear around these different ways to power it.

[tatulea]

I think my CP is 1910, so it should be ok.

Regarding outputting 3.3v back into my VDD net, that shouldn't be a problem I think.
Yesterday I had a problem because I had 2.6V on my VBUS when nothing was connected to the USB. I cut the trace between my VDD net and the VDD pin of CP and the voltage not on my VBUS is 0.4V.

Unfortunately, I cannot solder the VIO to VDD now on my board as the pin is too small.

Regarding the EN capacitor, I think I have to use it because mt reset doesn't want to work without ti at all. I will test that again.