100K spi transactions per second

[StefanRvO]

Hi.
I want to sample from an MCP3002 SPI ADC 100K times per second.

I'm currently using the following code and only archiving about 40000 (20K for each ADC channel) samples per second.

https://gitlab.com/StefanRvO/light-equa ... /mcp3002.c

It seems that there is a large interval between each transaction, which is causing this.
According to the SPI driver specification, there is a 25µs interval between SPI transaction, so i guess it will not be possible to get much higher than that this way.
Does anyone know some tricks to decrease the time?

I'm considering to enable Quad SPI and using one of the additional signals to simulate the CS pin and thus doing multiple samples per transaction, but this will create chuncks of transaction whit a large interval between. Does anybody have any better ideas, optimally with equal time between samples?

Regards
Stefan

[mikronauts]

That code sets the spi clock to 1.5Mhz, whereas the mcp3002 spec allows for 3.2mhz at 5vdc.

Run the adc at 5v, use a voltage divider on miso, and increase the spi clock.

Hi.
I want to sample from an MCP3002 SPI ADC 100K times per second.

I'm currently using the following code and only archiving about 40000 (20K for each ADC channel) samples per second.

https://gitlab.com/StefanRvO/light-equa ... /mcp3002.c

It seems that there is a large interval between each transaction, which is causing this.
According to the SPI driver specification, there is a 25µs interval between SPI transaction, so i guess it will not be possible to get much higher than that this way.
Does anyone know some tricks to decrease the time?

I'm considering to enable Quad SPI and using one of the additional signals to simulate the CS pin and thus doing multiple samples per transaction, but this will create chuncks of transaction whit a large interval between. Does anybody have any better ideas, optimally with equal time between samples?

Regards
Stefan

[StefanRvO]

I have attached a scope shot with the Chipselect and clock lines.

As you can see, the issue is not the clock speed, but rather the long intervals between transactions.
I don't think raising the clock speed would increase my sampling rate by more than maybe 20%, and there is some practical reasons in my PCB which means that i would like to avoid needing to create a 5V supply

[mikronauts]

15us intervals do seem excessive.

Perhaps there is a configurable parameter in the spi master library or the rtos for minimum cs enable/disable periods?

If not, maybe you could use the ulp to handle the spi transactions?

Or use interrupts for spi receive and handle them on the other core?

Worst case, write your own spi handler.

I have attached a scope shot with the Chipselect and clock lines.

As you can see, the issue is not the clock speed, but rather the long intervals between transactions.
I don't think raising the clock speed would increase my sampling rate by more than maybe 20%, and there is some practical reasons in my PCB which means that i would like to avoid needing to create a 5V supply