Multiple SPI slave: MISO tristate output?

[damian]

I need to connect multiple ESP32 as SPI slave in parallel configuration. One master drives MOSI, CLK, and multiple CS, on the other hand slaves are connected to the same MOSI and MISO bus. Now the question is:

is the MISO output automatically trisated when the CS of a specific slave becomes high?

If not, is the only solution to correctly drive the MISO line the addition of a tristate buffer (enabled by the respective chip selection line) in series with each MISO output?

[PeterR]

Most SPI slaves will tri-state when CS is high, but not all.
This article should help: https://www.dorkbotpdx.org/blog/paul/be ... in_3_steps

[damian]

Of course my question was about the ESP32 implementation of the spi slave interface.

Anyway, I saw that once the bus is initialized by spicommon_bus_initialize_io the MISO line has a bizarre behavior:

• when CS is high MISO output is driven low
• when CS is low and no transaction is in progress MISO output is driven high

So it seems that the MISO output of spi slave is never tristated.

[PeterR]

Did you try gpio_set_pull_mode()?
Think I remember reading that GPIO defaults to high pull up & your reports suggests that the SPI module switches direction only when selected.

[damian]

After some current measurements it seems that the MISO output stage is driven low or high depending on the level of CS (driven, not pulled up or down). So, no automatic tristate when CS is high...

Behavior update: if there's a transaction queued by the spi slave driver, MISO remains driven low even after CS goes low. If there's no transaction queued, my previous analysis is valid.

[rikkertkoppes]

Have you ever solved this problem? In now have a number of boards with direct spi lines between esp32 pico's, expecting "normal" spi miso behaviour (releasing the miso line when cs is high). Communication with multiple devices will not work as they are all asserting the same line.

I am looking for a software solution to this, as the hardware is already done