Is there a way in ESP32 Xtensa assembly to change the content of an address location by "dirting" only one register?

[djixon]

I've searched in Xtensa ISA doc but can not find any instruction which would perform anything with content of an address (its value is stored in one register), which then imply that for changing of some memory location at least two registers must be "dirted" something like

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 movi a1, address
 l32i  a0, a1, 0   // take the content in another register
 add  a0, a0, 1   // let's say increment it
 s32i a0, a1, 0   // store back new content

Did I miss something or it is just impossible to do it by "dirting" only one register? Something like:

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 l32i  a0, address, 0   // take the content of address
 add  a0, a0, 1   // let's say increment it
 s32i a0, address, 0   // store back new content to address

[MicroController]

No, that's not possible.
One reason is that addresses are 32 bits wide, and our Xtensas' instructions are between 2 and 3 (4) bytes in size. There just isn't enough room in an instruction to encode the instruction and 32 bits of an immediate.

[djixon]

I thought maybe there is some trick to store variable in IRAM (lets say right after ret instruction, or before routine entry point) and use some relative addresing to PC (which then could fit inside 24 bits OP code format size) but there is no such addresing mode which utilize only literal offset (without register). Also possible way would be to target address in cache and then using literal offset access to that value without utilizing register for address. Offcorse, reading would be into some register but that way it would be only one utilized. Also posible way would be to use some special register for address index (similary like indexed addressing is performed on microcontrollers). So you would use lets say

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movi a0, addres
wsr a0, some special register
l32i a0, that special register in indexing address mode
inc a0
s32i a0, that special register for indexing addres mode  

Aniway, thanks for info. Now, at least, I know that I didn't miss anything.

Also one more instant question, is there any document describing register policy in ISR? For example what registers are automaticaly preserved and how, what registers can be changed and what registers must not be changed and so on. Are there some registers strictly reserved by ESP-IDF. I mean, for examle, when a higher priority interrupt, interrupts some executing ISR of lower priority interrupt what registers are preserved in such a call of higher priority ISR?

[ESP_Sprite]

Also one more instant question, is there any document describing register policy in ISR? For example what registers are automaticaly preserved and how, what registers can be changed and what registers must not be changed and so on. Are there some registers strictly reserved by ESP-IDF. I mean, for examle, when a higher priority interrupt, interrupts some executing ISR of lower priority interrupt what registers are preserved in such a call of higher priority ISR?

All of them (except coprocessor registers, so no FPU) get preserved.

[djixon]

That is nice. So in custom ISR all are free for usage without any care for preservation/restore (not counting FRs).

I also see RER/WER instructions are supported in all ESP32/S2/S3. Is there any documentation where it is described how those EXTERN registers are used with the rest of out-of-core hardware? Since their implementation is not defined by XTENSA ISA, but are left to designer (in this case Espressif) custom implementation, and those RER/WER instructions reads/writes to processor ports it would be helpful knowing how many of them are used by Espressif and are there any free? Also where those ports are connected/directed? Can they be used to address or access out-of-core hardware which is presented in Espressif chip?