Continuous reset esp32-c3

[iceMan806]

Hello
I have designed an iot device using esp32-c3 and quactel mc20 module.
I have a big problem!
When the mc20 module is without a SIM card, the esp32 continues to work without problems. But when the SIM card is placed on the device, after a few seconds esp32-c3 starts to reset with a cycle of approximately 3-4 seconds.
When I search for the reset reason with the esp_reset_reason() function, it returns 0.
Interestingly, if I remove the crystal bypass capacitors, the situation will improve (10pf), but after a while, this problem occurs again.
One more thing, when I put my hand on the esp32-c3 crystal, the device resets!
---
The designed board is 4 layers.
thanks for your help

[ESP_Sprite]

Possibly a power issue? I know that GSM modules can use a pretty large burst of power while making a connection; could be that something is browning out.

[iceMan806]

I checked the power supply with an oscilloscope, there is no change, even if browning out, it should write the reason for the reset.
The important point here is that by removing the crystal capacitors, this problem will be fixed to some extent.
Only when we don't have crystal capacitors, Bluetooth doesn't work!

[ESP_Sprite]

Do you have serial logs? Can you post them? Also, can you post the schematic?

[iceMan806]

Unfortunately, I only have the USB connection and I cannot see the log(Because the micro is reset. The usb port is reset and the initial log of the device is lost, if you have a way to get it, tell me), but if you need a special register, I will print it separately. Yes, I will send you the schematic

[ESP_Sprite]

Really, no way to even solder a wire to the 499R resistor on U0TXD and get the logs from there?

Do you have C29 installed? If not, you could try to install that, see if it makes a difference.

[iceMan806]

With the method you said, I was able to get the log, only one was mixed with my data, in any case, I separated one from the log, if you need I can send you most of it (2-3 minutes).
It is not possible to install C29, because it is masked inside the schematic and not inside the pcb, if you doubt it, I will install it manually.

log:

.ESP-ROM:esp32c3-api1-2 !.207
Build:Feb...’‚....ÍÑé0x13..*Š%.%E5}IMQ¥,boot:0xd..*._F.ST_FLASH_BOOT)
S@.WP: `ee
mode:DIO,.clock div:1
hoad:0p3fcd61 .«¹é0x172c
load:0p4 3ce0 ..•¹é0x928
ë+‘é0p403d..«¹é0x2ce0
dntry .`4 3ce0 ....[0;32mI..¤J..¸½Ñé ES@-IDF.Ñ.4-dev-2825-gb63ec47238.`‘.,W•Bootloader.[0m
.[0;32mI.¤
.ë‹é compile `ime 1":1 0 .[0m
.[0;32mI (3!).ë‹é chip.`evision: 4.[0m
.[0;32mI.$S.½½Ñ}½µµé chip •Ù¥Í¥½¹é 4,.+ËË..½½Ñ±½…‘•Éc`ip revision: .[0m
.[0;32mI !!.당esp32c3: S.I S@eed...m[0m
.[0;32mI..°J..당esp32c3: S.I.ode .j´.j5
.[0;32mI..SJ.당esp32c3: SPI..Í¡.ªK•:.`..[0m
.[0;32mI..55).ë‹é Enabling RNG.early entropy source....[0m
.[0;32mI .SJ.ë‹é PArtition Table:.[0m
.[0;32mI..¢J..ë‹é ##.Label..• ....•SP.ʙ͕с L°Ñ¡m[0m
.[0;32mI. 72).ë‹é ..bÑ́..a.data..0 ´.j5
.[0;32mI .SJ.oot: .‹…‘…Ñ… ......@.‚‚‚+j5
.[0;32mI .¸J.oot: . .À}¥¹¥Ñ.... ...Š. .h5
.[0;32mI..‚J..not: .$‹…}Á........ .j5
.[0;32mI (1.H.ë‹é .‹…}Å ...A.a.L‚. 0.+j5
.[0;32mI...J.½½Ñé ..¥Ñѱ•™Í..­¹½Ý¹data .‚.ˆ‚.+j5
.[0;32mI .ˆºJ.€ë‹é End ˁ@Artition table.[0m
.[0;32mI (. !).ë‹}½µµé chip revision: 4, min. A@`lication chip Bevision: 0.[0m
.[0;32mI.&J.s`_image: segment 8....Éõ0 . ..¢…..Éõ3c09002.¥é•õ19bb8`.M....m[0m
.[0;32mI 53) esp_image: segment 1: paDdr=00 9be0.…‘‘Éõ0000..…é•õ00 3 h... .j5
.[0;32mI . 53).@sp_image: segment 2: @aDdr=00 29c18.W‘‘Éõ3fc8c00 .¥é•õ01548h...(....½…‘m[0m
.[0;32mI .MNJ*ÍÁ}¥µ…•é segment 3: paddr=00 @168.taddr=40380 ..¥é•õ04eb0`.2 ...½…‘m[0m
.[0;32mI . 70) esp_image: segment 4:.@A@dr=0003 ...…‘‘Éõ420 ..20 ¥é•õ8814ch..MMÓÂÂJ.+m[0m
.[0;32mI (258) esp_image: segment 5: paddr=000b8174 vaddr=40384eb0 size=070fch (..Ê’¢J.load.[0m
.[0;32mI (264) esp_image: segment 6: paddr=000bf278 vaddr=5000 1 .®K•õ00010h.....J.ë+‘m[0m
.[0;32mI (268) boot: Loaded app from partition at offset 0x100 .[0m
.[0;32mI (270) Boot: Disabling RNG early entropy source....[0m
.[0;32mI (287) cpu_start: Pro cpu up..[0m
.[0;32mI (295) cpu_start: Pro cpu start user code.[0m
.[0;32mI (296) cpu_start: cpu freq: 160000 ..£+j5
.[0;32mI (296) cpu_start: Application information:.[0m
.[0;32mI (298) cpu_start: Project name: ..¥‰•ÍÁ¥‘™m[0m
.[0;32mI (303) cpu_start: App version: .Ú[0m
.[0;32mI (308) cpu_start: Compile time: ul 5 2023 05:36:18.[0m
.[0;32mI (314) cpu_start: ELF file SHA256: 0 0 000 . . ....[0m
.[0;32mI (320) cpu_start: ESP-IDF: .... .4.2-dirty.[0m
.[0;32mI (325) heap_init: Initializing. RAM available for dynamic allocation:.[0m
.[0;32mI (333) heap_init: At 3FC8E4F0 len 00031B10 (198 KiB): DRAM.[0m
.[0;32mI (339) heap_init: At 3FCC0000 len 0001F060 (124 KiB): STACK/DRAM.[0m
.[0;32mI (346) heap_init: At 50000020 len 00001FE0 (7 KiB): RTCRAM.[0m
««.....H×....„..½±Á¡¥¹‘•Ù¥•¹avl24.com.Ÿ7

[iceMan806]

hi,I added the capacitor but it didn't make a difference, I was able to get a better log and I realized that the cause of the reset was GLITCH_RTC_RST. Do you have a solution for this error?

ESP-ROM:esp32c3-api1-20210207

Build:Feb 7 2021

rst:0x13 (GLITCH_RTC_RST),boot:0xd (SPI_FAST_FLASH_BOOT)

SPIWP:0xee

mode:DIO, clock div:1

load:0x3fcd6100,len:0x172c

load:0x403ce000,len:0x928

load:0x403d0000,len:0x2ce0

entry 0x403ce000

[0;32mI (31) boot: ESP-IDF v4.4-dev-2825-gb63ec47238 2nd stage bootloader[0m

[0;32mI (31) boot: compile time 12:10:40[0m

[0;32mI (31) boot: chip revision: 4[0m

[0;32mI (34) boot_comm: chip revision: 4, min. bootloader chip revision: 0[0m

[0;32mI (41) boot.esp32c3: SPI Speed : 80MHz[0m

[0;32mI (46) boot.esp32c3: SPI Mode : DIO[0m

[0;32mI (51) boot.esp32c3: SPI Flash Size : 4MB[0m

[0;32mI (55) boot: Enabling RNG early entropy source...[0m

[0;32mI (61) boot: Partition Table:[0m

[0;32mI (64) boot: ## Label Usage Type ST Offset Length[0m

[0;32mI (72) boot: 0 nvs WiFi data 01 02 00009000 00004000[0m

[0;32mI (79) boot: 1 otadata OTA data 01 00 0000d000 00002000[0m

[0;32mI (87) boot: 2 phy_init RF data 01 01 0000f000 00001000[0m

[0;32mI (94) boot: 3 ota_0 OTA app 00 10 00010000 00100000[0m

[0;32mI (102) boot: 4 ota_1 OTA app 00 11 00110000 00100000[0m

[0;32mI (109) boot: 5 littlefs Unknown data 01 82 00210000 00100000[0m

[0;32mI (117) boot: End of partition table[0m

[0;32mI (121) boot_comm: chip revision: 4, min. application chip revision: 0[0m

[0;32mI (128) esp_image: segment 0: paddr=00010020 vaddr=3c090020 size=19bb8h (105400) map[0m

[0;32mI (153) esp_image: segment 1: paddr=00029be0 vaddr=00000001 size=00030h ( 48) [0m

[0;32mI (153) esp_image: segment 2: paddr=00029c18 vaddr=3fc8c000 size=01548h ( 5448) load[0m

[0;32mI (159) esp_image: segment 3: paddr=0002b168 vaddr=40380000 size=04eb0h ( 20144) load[0m

[0;32mI (170) esp_image: segment 4: paddr=00030020 vaddr=42000020 size=8814ch (557388) map[0m

[0;32mI (258) esp_image: segment 5: paddr=000b8174 vaddr=40384eb0 size=070fch ( 28924) load[0m

[0;32mI (264) esp_image: segment 6: paddr=000bf278 vaddr=50000010 size=00010h ( 16) load[0m

[0;32mI (268) boot: Loaded app from partition at offset 0x10000[0m

[0;32mI (270) boot: Disabling RNG early entropy source...[0m

[0;32mI (287) cpu_start: Pro cpu up.[0m

[0;32mI (295) cpu_start: Pro cpu start user code[0m

[0;32mI (296) cpu_start: cpu freq: 160000000[0m

[0;32mI (296) cpu_start: Application information:[0m

[0;32mI (298) cpu_start: Project name: libespidf[0m

[0;32mI (303) cpu_start: App version: 1[0m

[0;32mI (308) cpu_start: Compile time: Jul 5 2023 05:36:18[0m

[0;32mI (314) cpu_start: ELF file SHA256: 0000000000000000...[0m

[0;32mI (320) cpu_start: ESP-IDF: v4.4.2-dirty[0m

[0;32mI (325) heap_init: Initializing. RAM available for dynamic allocation:[0m

[0;32mI (333) heap_init: At 3FC8E4F0 len 00031B10 (198 KiB): DRAM[0m

[0;32mI (339) heap_init: At 3FCC0000 len 0001F060 (124 KiB): STACK/DRAM[0m

[0;32mI (346) heap_init: At 50000020 len 00001FE0 (7 KiB): RTCRAM[0m

[ESP_Sprite]

Ooh, that's the clock glitch detector. Means something is wrong with the (crystal) clock signal going into the ESP32. Potentially something from the GSM module is being coupled into the clock traces? You could also try disabling the glitch reset functionality by setting a bit in RTC_CNTL_ANA_CONF_REG (see the C3 TRM), that might be worth trying just to see if there are issues elsewhere.

[iceMan806]

Yes, I came to this conclusion, I will definitely test this item today, I have a lot of doubts about the crystal capacitors, so I will test it today.