yup.

The wording in errata 3.16 (plural workarounds ) would seem to imply that you either need to use a memw instruction / volatile keyword (which should be handled by the READ_PERI_REG macro), or insert 7 NOPs. So it doesn't explain this NOP (using READ_PERI_REG should be enough), or is there another re...

Hi,

I'm trying to figure out the reason behind the NOP in ESP32 uart_ll_read_rxfifo

https://github.com/espressif/esp-idf/bl ... _ll.h#L203

Is this related to esp32 errata 3.16 ?

Is there a reason why LWIP_TCPIP_CORE_LOCKING (and LWIP_TCPIP_CORE_LOCKING_INPUT) is disabled in current esp-idf versions? It's the default since LwIP v2. LwIP docs state that enabling this option is recommended. It is recommended to use LWIP_TCPIP_CORE_LOCKING since this is the way with least runti...

I don't think it's possible to continuously sample the ADC using I2S DMA. There is no working example in the esp-idf and many ADC registers are undocumented. It's either a hardware problem, or some crucial piece of documentation is missing. Either way, I've given up on using the I2S method. I've set...

There's also the undocumented register: union { struct { volatile uint32_t rstb_wait: 8; volatile uint32_t standby_wait: 8; volatile uint32_t start_wait: 8; volatile uint32_t sample_cycle: 8; /*sample cycles*/ }; volatile uint32_t val; }saradc_fsm; Which also seems to iteract with this. It seems it'...

A couple of more observations: 1. The selected sampling rate is not respected even in single channel mode. APB_SARADC_MAX_MEAS_NUM seems to affect the sampling rate. The WS clock output is at the expected frequency, but some samples seem to be skipped by the hardware. Some combinations, i.e. APB_SAR...

I'm having problems getting ADC pattern tables to work correctly with I2S DMA. The problems seem to be somehow related to APB_SARADC_MAX_MEAS_NUM in APB_SARADC_CTRL2_REG, which is not documented. I've posted about this on github: https://github.com/espressif/esp-idf/pull/1991 Sampling works, but the...