Thanks krzychb.

After some current measurements it seems that the MISO output stage is driven low or high depending on the level of CS (driven, not pulled up or down). So, no automatic tristate when CS is high... Behavior updat e: if there's a transaction queued by the spi slave driver, MISO remains driven low even...

Of course my question was about the ESP32 implementation of the spi slave interface. Anyway, I saw that once the bus is initialized by spicommon_bus_initialize_io the MISO line has a bizarre behavior: when CS is high MISO output is driven low when CS is low and no transaction is in progress MISO out...

I need to connect multiple ESP32 as SPI slave in parallel configuration. One master drives MOSI, CLK, and multiple CS, on the other hand slaves are connected to the same MOSI and MISO bus. Now the question is: is the MISO output automatically trisated when the CS of a specific slave becomes high? If...

After some experiments I saw that the removal of this RC circuit doesn't affect anything visible (I note that I don't use deep sleep in my application).
However I hope that the functionality of this circuit will be explained in an upcoming release of the official technical documentation.

I have doubts about the function of the RC circuit connected to CAP1 and CAP2. The only words about it are in ESP32 Hardware Design Guidelines : Removing the RC circuit may slightly affect ESP32 in Deep-sleep mode So the rc circuit is involved in the 8MHz internal oscillator used in deep-sleep mode?...