I have ran out of pins to use on the ESP32 therefore I am willing to set UART 1 and 2 RX inputs on GPIO 34,35 with an appropriate pull up resistor and change the corresponding UART RX pin(s) in software to the above. I need a second opinion if this would this work or not?

If I'm understanding correctly, you have an ESP32 serial connected to a PC and the ESP32 is running tests directed from the PC by user entry. What you want to be able to do is have a human "signal" that you wish to interrupt the test? I am also suspecting that there is a user written application ru...

Here is a recorded terminal session: https://asciinema.org/a/1sNPQn8cf3f3XRStNkNUJShZt In brief the ESP32 is connected over serial to my computer. I send initial configurations to as an SPIFFS filesystem on my computer. The reads the configurations and esp32 writes the results of the tests chosen ov...

I have the situation at hand whereby I have a battery of runtime tests that test say: 1. Communication 2. I/O among others. Some of the tests need to be run for a long time thus it would be good if posix signals were supported in the console component to end a test at user's will. Example ctrl-c (C-...

Solved. The code is fine and works with a SPI device connected. Logic analyser decoded MISO data is in agreement with that in tx_data array. Do not simulate data on the miso line with a signal generator!

Could you specify what branch you are on? I could test with the Heltec board I have.

Hi all, I am trying to setup tests for ESP32 full duplex, I am reading only a byte. I have the ESP32 connected to a protocol analyser and the MISO line is connected to a signal generator at a tenth of the frequency of the SPI clock to simulate data on the MISO line. Using the analyser I can see the ...

ESP_Sprite wrote:FWIW, on initialization of the SPI bus, you can specify the maximum amount of bytes for DMA transfers in max_transfer_sz in the struct you pass to spi_bus_initialize. This way, you can raise the 4094-byte limit you encountered.

Thanks for this Sprite.

Hi all, Thank you very much for your suggestions. For a bit of background info for anyone in future refferring to this. I previously would have the data and commands in a single buffer. with the command phase and address phase of the specific transaction unset. I therefore can see that there are two...

I have the an chip, the LoRa SX1301 that has a mode called burst mode, this allows the SPI host to read and write to several addresses as the SPI slave auto-increments the addresses internally. This avoids explicitly sending the address in subsequent transactions. The only requirement is that the CS...