Ok, so I looked into this more and came up with the following lines to disable the ADC from ULP. WRITE_RTC_REG(SENS_SAR_PERI_CLK_GATE_CONF_REG, SENS_SARADC_CLK_EN_S, 1, 0) WRITE_RTC_REG(SENS_SAR_PERI_CLK_GATE_CONF_REG, SENS_IOMUX_CLK_EN_S, 1, 0) WRITE_RTC_REG(SENS_SAR_POWER_XPD_SAR_REG, SENS_SARCLK_...

Sorry, I forgot to mention that I am using ULP-FSM not RISCV. Is the same possible there?

I am in too deep in this project now, I have to get it working. I would really like to try to turn the ADC on/off from ULP and thoroughly test it. Can someone tell me how I can implement that on the ULP?

Thank you very much. I don't have that much experience with ESPs yet, could you please explain a bit more what I need to do to implement your two approaches?

Thank you, that is a good test, should have thought of that myself. I removed everything that would cause changes after deep sleep and now all 4 batches are around 8 µA in deep sleep, as they should be. On one of the boards that had 50 µA before, I then re-activated step by step different parts that...

I have a serious problem with an ESP32-S3 based project, which needs to run a long time on a single battery. I have programmed everything using ESP-IDF 5.1.1 in Eclipse. The main program does some calculations, starts the ULP program and then we go to esp_deep_sleep_start(). The ULP periodically set...