Thanks a lot! It is a very useful hint that actually rx_bck_div_num is not used in parallel slave mode.

on a side note via commenting // logic_analyzer_ll_set_clock(sample_rate); actually default values will be applied according the ESP32 technical reference manual. The default values are equivalent with these lines I2SX.clkm_conf.clkm_div_num = 4; I2SX.sample_rate_conf.rx_bck_div_num = 6; ... actuall...

I have recently managed to port this nice project to latest esp-idf: https://www.esp32.com/viewtopic.php?t=3256 This works very well. However if I try to switch the external clock (slave mode), then there is no output. The Technical Reference says that arbitrary combination of input/output vs. maste...

I had to do the following changes for slave mode (using external clock) on ESP32:
It seems to capture sd interface signals stable with 20 MHz clock.

Thanks a lot! Static 40 MHz sample rate seems to work fine for my use case. I would also like to send packages at 40 MHz as a kind of automation. I will try to figure out how.

Thank you so much. I am using ESP32 (pico) in my project. Will the same work with that as well?

It sounds good. And can I use the CLK pin of the external sdmmc host as clock source instead of the internal clock?

Hi, I would like to use your logic analyzer for capturing CMD pin traffic of sdmmc interface. Is it possible to use CLK pin of sdmmc as clock source? sdmmc runs at 40 MHz in my case.