i found a possible cause since then.
https://github.com/apache/nuttx/issues/13761
i guess the use of pid 1 was a workaround for this problem.

thank you for the comment. but i don't think it explains.
in case of nuttx, pid 1 vs 5 is about userspace. the control registers are accessed by the kernel, which is always pid 0.

i noticed that, when using psram, nuttx uses pid 1 instead of pid 5.
https://github.com/apache/nuttx/blob/82 ... .h#L64-L65
does it imply that pid 0/1 have something special wrt cache/mmu?

hi, i'm experimenting to use pid controller to switch mmu mappings for external memory. (my current focus is spiram, not flash) i have a few questions. * is this a viable approach at all? (known erratas etc?) * is the cache tagged with virtual address? (vivt?) * when using pid controller, does the c...

thank you.

i confirmed at least trivial cases works with modified nuttx.

hi, reading the ESP32 technical reference manual, it seems that the MMU for the external memory can be programmed to use different virt-to-phys mappings for CPUs. (26.3.2.2) am i reading it correctly? if so, is it expected to actually work? ie. is there any software using the feature? i'm wondering ...