Search found 6 matches
- Thu Jul 25, 2024 6:52 pm
- Forum: General Discussion
- Topic: SPI sck synchronization
- Replies: 7
- Views: 2846
Re: SPI sck synchronization
Thank you for the suggestion. I'm trying to use SPI and read from the intan RDH headstage with 128 channels, here's the datasheet: https://intantech.com/files/Intan_RHD2000_128_channel_headstage.pdf And here's the adapter board I'm using to connect the headstage to the microcontroller : https://inta...
- Mon Jul 22, 2024 6:51 pm
- Forum: General Discussion
- Topic: SPI sck synchronization
- Replies: 7
- Views: 2846
Re: SPI sck synchronization
Hi, on the esp32-s3 datasheet v1.8, it says "• 8-line SPI mode supports single data rate (SDR) and double data rate (DDR)" (page 36 at the bottom under the "Features of SPI0 and SPI1" section). https://www.espressif.com/sites/default/files/documentation/esp32-s3_datasheet_en.pdf Does that mean that ...
- Fri Jul 19, 2024 11:30 pm
- Forum: Hardware
- Topic: ESP32-S3 DDR SPI
- Replies: 8
- Views: 8165
Re: ESP32-S3 DDR SPI
Hi, is there an update with the project? I'm trying to do the same intan headstage spi communication.
- Fri Jul 19, 2024 5:37 pm
- Forum: General Discussion
- Topic: SPI sck synchronization
- Replies: 7
- Views: 2846
Re: SPI sck synchronization
Hi, did some more research into the esp32 s3 chip, and I have a few questions. First, what does the 8 line DDR mode mean? does that mean there's 8 parallel data lines like MISO1, MISO2, MISO3, and MISO4, as well as MOSI1, MOSI2, MOSI3, and MOSI4? Secondly, can the SPI buses be configured so that CS ...
- Tue Jul 16, 2024 4:02 pm
- Forum: General Discussion
- Topic: SPI sck synchronization
- Replies: 7
- Views: 2846
Re: SPI sck synchronization
Thank you for your help! I'll try out your solutions and hopefully it works!
- Mon Jul 15, 2024 10:17 pm
- Forum: General Discussion
- Topic: SPI sck synchronization
- Replies: 7
- Views: 2846
SPI sck synchronization
Hi! I'm using a esp32-WROVER-IE and Arduino IDE for programming. I'm trying to read from the Intan RHD Recording Headstages, which send data on both the rising end falling edge of the SCK. To read during the rising and falling edge, I'm trying to use both VSPI and HSPI, but delay one of the SCK by h...