Search found 7 matches

by wxd2024
Sun Sep 15, 2024 9:19 am
Forum: ESP-IDF
Topic: How to bind a socket to specific net_if
Replies: 0
Views: 312

How to bind a socket to specific net_if

Greetings, I am using both ethernet and wifi in the current project. Does setting the default net_if to one of the two before each time socket connect is called force the socket to be bound with the specific net_if? Assume the target ip address is in an ip section of neither net_ifs and and ip_v4 ro...
by wxd2024
Wed Aug 21, 2024 5:12 am
Forum: ESP-IDF
Topic: Any methods to check data in uart tx fifo has already been sent
Replies: 4
Views: 850

Re: Any methods to check data in uart tx fifo has already been sent

Yes, I think so. Maybe there is some other reasons causing my problem. I will check it again.
by wxd2024
Tue Aug 20, 2024 4:30 pm
Forum: ESP-IDF
Topic: Any methods to check data in uart tx fifo has already been sent
Replies: 4
Views: 850

Re: Any methods to check data in uart tx fifo has already been sent

Dear aliarifat794

Thanks a lot for the help. Both checking UART_TX_DONE status bit and adding a delay before sending the next byte are promising solutions. For checking the status bit, could you give some hints on how to get it, since I can't find any info in the idf document.

Best regards
by wxd2024
Tue Aug 20, 2024 12:41 pm
Forum: ESP-IDF
Topic: Any methods to check data in uart tx fifo has already been sent
Replies: 4
Views: 850

Any methods to check data in uart tx fifo has already been sent

Greetings,

Is there any methods to check the data that is written into uart tx fifo has been sent out by the hardware after calling uart_hal_tx_fifo_write(). It seems UART_TX_DONE interrupt just indicates tx fifo is empty instead of assuring the data has been actually sent out.

Regards
by wxd2024
Fri Aug 16, 2024 10:29 am
Forum: ESP-IDF
Topic: Interrupt occurs during cpu reading uart rx fifo register mentioned in esp32 SoC errata 3.21
Replies: 0
Views: 437

Interrupt occurs during cpu reading uart rx fifo register mentioned in esp32 SoC errata 3.21

Greetings, SoC platform:esp32-U4WDH idf version:v4.4 After reading the esp32 SoC errata, I come up with a question regarding the problem stated in section 3.21. It says when cpu reading five specific FIFO register addresses, if interrupts occur, the reading process will be interrupted and subsequent...
by wxd2024
Mon Jun 24, 2024 9:25 am
Forum: ESP-IDF
Topic: Level 5 interrupt causing core0 paniced due to interrupt wdt timeout
Replies: 3
Views: 744

Re: Level 5 interrupt causing core0 paniced due to interrupt wdt timeout

Dear MicroController, Thanks a lot for the reply, thought the topic has sunk. Using a14 to store gpio address for further toggling is indeed what should've been done and I will make the correction. Besides this, since I am not familiar with using assembly language and the code's frame was adopted fr...
by wxd2024
Thu Jun 20, 2024 9:41 am
Forum: ESP-IDF
Topic: Level 5 interrupt causing core0 paniced due to interrupt wdt timeout
Replies: 3
Views: 744

Level 5 interrupt causing core0 paniced due to interrupt wdt timeout

Hi, chip: esp32-U4WDH IDF version:v4.4 with commit 8153bfe412 platform: vscode on linux description: Need low latency gpio interrupt, so wrote the following code in assembly to test the feasibility. ETS_GPIO_INTR_SOURCE is linked to number 31 of the interrupt matrix using intr_matrix_set(). The trig...