Search found 31 matches

by hwmaier
Fri Mar 04, 2022 9:26 am
Forum: General Discussion
Topic: Impressive Ethernet bandwith using ESP32
Replies: 5
Views: 56502

Re: Impressive Ethernet bandwith using ESP32

ESP32 internal MAC + external PHY. You won't achieve those transfer speeds with external MACs.
by hwmaier
Tue Sep 03, 2019 5:59 am
Forum: Hardware
Topic: Using Ethernet LAN8720 and I2S Audio at same time
Replies: 7
Views: 12031

Re: Using Ethernet LAN8720 and I2S Audio at same time

Only saw you post now, so my answer may not be relevant anymore but may help others in the future. If you use Ethernet, GPIO0 is taken either as clock input or output and CLK_OUT1 cannot be used other than for 50MHz. You are also limited in the clock frequencies you can configure for I2S if the APLL...
by hwmaier
Thu Nov 30, 2017 7:11 am
Forum: General Discussion
Topic: APLL / GPIO16_EMAC_CLK_OUT - wrong frequency - unable to generate 50MHz clk with rev0 chip
Replies: 2
Views: 7494

Re: APLL / GPIO16_EMAC_CLK_OUT - wrong frequency - unable to generate 50MHz clk with rev0 chip

And your code works as well once the order of initialization is modified. See below code which outputs nice 50MHz on GPIO16. // Enable the I2S peripheral periph_module_enable(PERIPH_I2S0_MODULE); // // Configure Audio PLL to 100 MHz. // Note: sdm2 seems limited to 12 for some reason. // // f_xtal (s...
by hwmaier
Thu Nov 30, 2017 6:49 am
Forum: General Discussion
Topic: APLL / GPIO16_EMAC_CLK_OUT - wrong frequency - unable to generate 50MHz clk with rev0 chip
Replies: 2
Views: 7494

Re: APLL / GPIO16_EMAC_CLK_OUT - wrong frequency - unable to generate 50MHz clk with rev0 chip

I managed to generate clean 50MHz using the Audio PLL and I2S using the following code. Signal is routed to GPIO0. // Enable the I2S peripheral periph_module_enable(PERIPH_I2S0_MODULE); // // Configure Audio PLL to 100 MHz. // Note: sdm2 seems limited to 12 for some reason. // // f_xtal (sdm2 + sdm1...
by hwmaier
Tue Sep 12, 2017 12:58 am
Forum: General Discussion
Topic: What would you like to see in The Next Chip?
Replies: 443
Views: 930512

Re: What would you like to see in The Next Chip?

- Support for larger flash memory or support for adding a 2nd flash memory chip to extend flash - USB - CAN bus with a slower clock source so we can support all standard CAN bitrates (currently 10kbps and 20kbps are not possible) - 2 more UARTs (once you add a 4G modem and GPS you quickly run out of...
by hwmaier
Sun Aug 06, 2017 11:41 pm
Forum: ESP-IDF
Topic: RS-485 support
Replies: 27
Views: 62277

Re: RS-485 support

@fri.sch Most of the support I added is for half-duplex operation, so you must not send while receiving and you must wait until the other sender is quiet before your side starts sending. Otherwise you get collisions and the data will be garbled.
by hwmaier
Fri Jun 16, 2017 7:43 am
Forum: ESP-IDF
Topic: RS-485 support
Replies: 27
Views: 62277

Re: RS-485 support

@aaquilina Today I started working on the RS-485 code again, and I also have this phantom null character at the end of each transmission. I investigated this further with different line driver circuits. Circuit A) +---------------+ RX <-------| R | | B|---- TX ------->| D MAX485 | ESP32 | | RS-485 s...
by hwmaier
Wed Jun 14, 2017 1:18 pm
Forum: Hardware
Topic: CAN controller clock and slow CAN bitrates
Replies: 15
Views: 27677

Re: CAN controller clock and slow CAN bitrates

Thanks to both rudi and ESP_igrr for all the info and clarifications provided in this thread.
by hwmaier
Wed Jun 14, 2017 10:41 am
Forum: Hardware
Topic: CAN controller clock and slow CAN bitrates
Replies: 15
Views: 27677

Re: CAN controller clock and slow CAN bitrates

Would the Ethernet still work with lowered APB Clock ? I would expect it as the clock comes from an external source.