Hello, In the deep sleep mode, if we power up the XTAL, I was curious if it's possible for the ULP to access the 40 MHz XTAL as RTC_FAST_CLK. In the header soc/clk_tree_defs.h, there appears to be an option. /** * @brief RTC_FAST_CLK mux inputs, which are the supported clock sources for the RTC_FAST...