Hello, can somebody explain details about the I2S_TIMING_REG register values (see 12.8 in the datasheet ? Especially concerning the following: what are the cycles referenced for e.g. I2S_RX_SD_IN_DELAY . Is it BCK cycles? or I2Sn_CLK cycles? what is the meaning of I2S_RX_DSYNC_SW? which signals are ...