Search found 4 matches
- Tue May 16, 2023 6:30 am
- Forum: ESP-IDF
- Topic: Problem with gcov example
- Replies: 0
- Views: 702
Problem with gcov example
When I try to build the gcov example, I get the following output. Other examples build ok. Any ideas? $ idf.py build Executing action: all (aliases: build) Running cmake in directory /home/xxxx/yyyy/gcov/build Executing "cmake -G Ninja -DPYTHON_DEPS_CHECKED=1 -DPYTHON=/home/xxxx/.espressif/python_en...
- Wed Feb 08, 2023 2:27 am
- Forum: ESP-IDF
- Topic: ESP-IDF and Xtensa instructions S32C1I, L32AI and S32RI
- Replies: 4
- Views: 1763
Re: ESP-IDF and Xtensa instructions S32C1I, L32AI and S32RI
Thanks ESP_Sprite. Just to further clarify with a couple of examples. Will variable "y" ever receive a scrambled value or are 32bit reads and writes are always atomic? - Assuming process1 and process2 are running on separate cores - Assuming process1 and process2 are running on same core, process2 h...
- Wed Feb 08, 2023 1:15 am
- Forum: ESP-IDF
- Topic: ESP-IDF and Xtensa instructions S32C1I, L32AI and S32RI
- Replies: 4
- Views: 1763
Re: ESP-IDF and Xtensa instructions S32C1I, L32AI and S32RI
Thanks ESP_Sprite.
Ok so just to be clear, by using std::atomic, the compiler will implement by using compare-and-swap rather then stop interrupts?
Ok so just to be clear, by using std::atomic, the compiler will implement by using compare-and-swap rather then stop interrupts?
- Tue Feb 07, 2023 11:07 pm
- Forum: ESP-IDF
- Topic: ESP-IDF and Xtensa instructions S32C1I, L32AI and S32RI
- Replies: 4
- Views: 1763
ESP-IDF and Xtensa instructions S32C1I, L32AI and S32RI
Hi, I am new to programming ESP-IDF. Been reading the documentation and I have some questions. Note that I am not concerned about high level synchronisation that stops interrupts, rather I am interested in how the framework uses XTensa native instructions to support synchronisation. The ESP32S3 API ...