Initializing the setup structure seems to fix the problem.
I think it could be the beacon timing that is set to an arbitrary value due to the missing initialization.

Sirs I am having problems with connecting my iPhone8 to the espressif access point. Around only one out of five attempts are successful. I have set logging to "INFO" but the information I get does not make me wiser. I have traversed the posts and have found an issue from 2015 reassembling this probl...

Hi
Just wondering..
Does anyone knows why Espressif framework comprise three instances of python.exe in the ".espressif" folder?
Thanks in advance!
Br Søren

Hi
Thanks for your replies
Is it correct that a cache miss in the PSRAM area just triggers functionality implemented in the Espressif "spiram_psram.c" module?
And thereby only stalls the current thread accessing the PSRAM?
Thanks in advance!
Best regards Søren

PSRAM access by itself doesn't stall both cores, only the core that is affected. However, what you may be seeing is that PSRAM and flash use the same bus, and as such the processor not using psram will be stalled on a cache miss as it needs to wait for the PSRAM access to finish before it can do a ...

Hi I need to reserve one CPU core for critical interrupt and WIFI handling. When I use PSRAM the CPU core accessing the PSRAM will get stalled until PSRAM data transmission is concluded. How can I configure ESP-IDF to only allocate PSRAM for one CPU core so the other CPU core won't get stalled due t...

Using a JTAG debugger I observe that a UserException is thrown when I try to single step over the "lsi f0,a1,96" instruction. The rsr.exccause reports 32, equal to Coprocessor0Disabled exception. The symptom in the system is that after haing executed the code comprising the "lsi f0,a1,96" instructio...