useful benchmark of different memcpy techniques. For anyone who might find this interesting, the code we built for this is on GitHub here and the benchmarks are below. Works with an ESP32-S3-WROOM-1U-N8R8 (Octal SPI PSRAM). Should work with any configuration of the ESP32-S3 with external RAM but th...

That math ain't mathin'... Haha. OK let me see... 128 bits = 16 bytes 240 Million clock cycles x 16 bytes = 3,840 Million bytes per sec Half = 1,920 Million bytes per sec. OK, I must have been on a different planet. :shock: I was going to ask where I find the documentation on the instructions used ...

Check out my pull request :) Perfect! Interesting to see the 16 byte version stalling a bit more. According to your comments this is due to the CPU's pipeline architecture. By my math, with the CPU operating at 240 MHz moving 128 bits (16 bytes) per clock cycle it should be able to read 15 GB/s (1,...

Using standalone assembler files (.S) is the opposite of what I want. Writing algorithms in assembler on top of manually implementing the ABI, managing register allocation, data types, optimizations &c. is unnecessarily complicated, as it makes you replicate what the compiler will do automatically ...

That's just because my GB is 1000000000 bytes and yours is 1024*1024*1024 ;-). Bytes/1000 cycles are identical. I wondered that but hadn't done the math. Nice! Thanks for helping me figure out how to get max bandwidth from the CPU! It would be nice if the GDMA controller had access to the IRAM with...

A generic memcpy function, like implemented in the DSP lib, must be able to deal with all kinds of unaligned memory addresses as input and this necessitates some overhead which may contribute to it appearing a little slower than theoretically possible. Its a lot slower! It does support using a zero...

For me it boils down to a) inline assembler and b) ways to 'smoothly' integrate the use of inline assembly into C++ code. Funny how one's C++ experience defines what they prefer. I like the inline assembly as there is no need to understand the inner workings of the GCC compiler in order to understa...

Very nice, however I can't get the code to compile as it doesn't recognize the RPT (Cadence Tensilica Extensions - repeat instruction I think?), or Q0 and Q1 (PIE registers). What header do I need to add for the C++ compiler to recognize these? Also where is the documentation explaining how to use t...

With minor tweaking I actually get 7972 IRAM bytes copied per 1000 CPU cycles via the CPU, i.e. actual 1.91GB/s. On an MCU which costs less than €2 :o Amazing! WOW that's impressive and worth knowing. I didn't realize the ESP32 had a 128 bit memory bus. Too cool. I just wish it had a larger interna...

BTW: In order to make the code compile on my PC I had to get the PSRAM Cache Line Size using this version of the command when I used the Master branch. const uint32_t PSRAM_ALIGN = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_DATA); On my ESP32-S3-WROOM-1U-N8R8 with the main cloc...