i have 2 reason. 1. srec binary flash through OTAP. (OTA binary transmitted by BT and written to specific partition). Our OTAP tool is designed to transfer srec binary 2. In order to handle the 1st method, i thought of using srec binary flash over idf.py. But i assume the idf.py is designed to trans...

Team,

Can we flash srec file format to ESP32? I tried but it didnt work. So thought of checking here... Is there anything specific i need to do inorder to make it work with srec file?

Team,

Any input on this query? I had to use SIP flash (SPI0/SPI1) as well as external flash (SPI2). I am using esp32s3 chip

Team,

Can i use SPI2/3 in custom bootloader? Given drivers in bootloader seems supporting only SPI0/1 (memory mapped SPI). Let me know if we can access SPI2/3 also provide which files & interfaces i can use

Unless if i update the build structure as below, then it is compiling without error. Because the CMakelist.txt inside bootloader/subproject is referring custom bootloader path as "${PROJECT_SOURCE_DIR}/bootloader_components". ├── main │ ├── CMakeLists.txt This is main cmakelist.txt and it references...

@ESP_Igrr, Thanks for your reply. I tried custom bootloader override example but i face the below error. c:/espressif/tools/xtensa-esp32s3-elf/esp-2021r2-patch3-8.4.0/xtensa-esp32s3-elf/bin/../lib/gcc/xtensa-esp32s3-elf/8.4.0/../../../../xtensa-esp32s3-elf/bin/ld.exe: appl.elf section `.dram0.bss' w...

Team, I have copied bootloader folder from <esp_sdk>components to myproject/components. I modified the necessary changes so that it can generate pbl.bin in build/pbl/pbl.bin. But i could not avoid generating bootloader.bin. The assumption is to use this customized pbl.bin instead of bootloader.bin. ...

Is there any input how to debug second stage bootloader? We are using eclipse to debug the application. when we change the elf to bootloader, we are unable to debug 2nd stage bootloader. we tried placing breakpoint at startup (call_start_cpu0) but it never hits and enters to application.

I have 1 update with respect to the above. I have executed the above example in evaluation board (esp32s3 evk). with evaluation board connected through a external power supply, it consumes 1.2mA during deep sleep. Is this expected value? The same example in my custom target consumes 8mA. If the valu...

With deep_sleep example which you specified also i see same 8mA current consumption. The sleep wakeup source in deep_sleep example which i used is ext0. In ulp_riscv/gpio example wakeup source is ulp. I can see the different wakeup sources (using esp_sleep_get_wakeup_cause()) with same reason (DSLEE...