I try to reduce the power consumption of an ESP32-S3 by running only a single core. I've checked "Run FreeRTOS on on first core" in the FreeRTOS options. The log shows that the system is indeed running in single core mode, however, the current consumption does not change a bit. According to the data...

That seems to be a nicer solution indeed. However, then you'd need to add this component to all the components explicitly. While I could do it for my own components, it does not work with system or managed components like NimBLE or TinyUSB, I believe. On the other hand, the "include_directories" met...

Now, how to do the same for ULP-RISCV components? Apparently the method above does not work with the RISCV compiler.

I have figured it out. Add
to the CMakeList.txt in the project's root directory, right before:

My intention is to keep all product-specific configuration header files in a single directory, for example, in the 'main/include' directory. I have several reusable (not product-specific) components that need to access these header files. I did not find any hint in the documentation about how to spe...

Yes. However, there is only one integrated USB PHY on chip, so you would need an external PHY for the other function. See pp. 942. of the Technical Reference Manual v0.8.

That’s good news, thank you for the clarification!

Ahhh, I missed the “each CPU” part. Thank you for the clarification!

I did not find a definitive answer in the current documentation: how is simultaneous SRAM access by the two cores handled? Is the internal SRAM dual-ported (I mean that the two cores can address and access the same SRAM without additional wait states), or is there some kind of arbitration, making it...

I did not find a definite answer in the current documentation: does each core have an independent FPU, or is it shared between the cores?